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OXCFU950 DATA SHEET
FEATURES
* * * USB/UART multi-function 16-bit PC Card device Host interface * 16-bit PC Card (PCMCIA revision 8.0) compliant * CompactFlash/CF+ (revision 3.0) compliant USB host controller * Supports USB 2.0/1.1 full-speed compliant (12 Mbps) & low speed (1.5 Mbps) devices * 8-Kbyte data buffer * Integrated OHCI-like controller supported by Oxford Semiconductor drivers * Supports control, bulk, interrupt & isochronous transfers * Supports USB PORT_OVER_CURRENT & PORT_POWER signals via MIO pins Integrated USB PHY transceivers Flexible OX16C95x-based UART * Supports 450 up to 950 (fully programmable) * Baud rates up to 12 Mbps * 128-byte deep transmit/receive FIFO * Software-compatible with standard 16C550 * Readable FIFO levels * 9-bit data framing as well as 5,6,7 & 8 * Detection of bad data in the receiver FIFO Optional wakeup from low-power mode Automated in-band flow control using programmable Xon/Xoff characters * Automated hardware flow control using CTS#/RTS# & DSR#/DTR# * Integral support for 4-byte I/O access for enhanced host-side data throughput 8-Kbitx8 EEPROM for CIS & default configuration. Programmable using Oxford Semiconductor utilities Power management for low-power operation * USB suspend & resume * UART sleep mode Single 12-MHz crystal oscillator for low power 4 multi-purpose I/O pins configurable as interrupts UART & MIO pins have variable I/O voltage levels from 1.8 V to 3.3 V nominal PC Card/CF+ I/Os are all 3.3 V with 5-V tolerance Single supply voltage range 2.85 V to 3.6 V Internal regulation for 1.8 V Supply current * Less than 4 mA idle * Less than 13 mA active Industrial temperature range -40C to +85C 64-pin QFN (9 mm x 9 mm) package * *
* * * * * * * * * * *
* *
DESCRIPTION
The OXCFU950 is a low-cost, synchronous 16-bit PC Card (PCMCIA) or CompactFlash/CF+ to UART and USB host controller. It combines the high performance of Oxford Semiconductor OX16C95x UART technology with USB host capabilities. The inclusion of both a UART and USB make the OXCFU950 ideal for wireless data cards. The OXCFU950 integrates an OHCI-based USB host controller, which supports a single USB port via the integrated transceiver. An 8-Kbyte memory provides an efficient interface for buffer and control structures between the USB controller and the device driver. The attribute memory, UART and USB registers can be programmed via the internal EEPROM during power up or hard/soft reset, allowing different card manufacturers to customize information contained in the attribute memory or UART/USB registers, for example PC Card ID value.
The 3.3-V technology has been specified to operate as low as 2.85 V to allow an in-line regulator to be used for mixed 3-V/5-V applications. CF/PC Card pins are 5-V tolerant and the variable I/O voltage to the UART/MIO pins eases the connection to application chipsets. A number of power-down modes are included to minimize power consumption, including sleep modes for when a device function is not being used. The OXCFU950 contains a single-channel ultra-high performance OX16C95x UART offering data rates up to 12 Mbps and 128-byte deep transmitter and receiver FIFOs. Deep FIFOs reduce CPU overhead and allow utilization of higher data rates. The OXCFU950 USB controller supports OHCI-compliant host stack software (available from Oxford Semiconductor). The OXCFU950 UART is software-compatible with the widely-used industry-standard 16C550 type devices and compatibles, as well as other OX16C95x family devices.
Oxford Semiconductor 1900 McCarthy Boulevard, Suite 210 Milpitas, CA 95035 USA
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The addition of software resets enable the device to recover from unforeseen error conditions, allowing drivers to restart gracefully. The OXCFU950 includes four user I/O pins to enhance external device control. These I/O pins can also be configured as interrupt inputs.
OXCFU950 DATA SHEET
For simplicity, the host interface is referred to as the CompactFlash interface throughout this specification. Unless otherwise stated, this should be taken to include PCMCIA 16-bit Card operation as well as CompactFlash/CF+.
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OXCFU950 DATA SHEET
CONTENTS
FEATURES ................................................................................................................................................... 1 DESCRIPTION .............................................................................................................................................. 1 CONTENTS................................................................................................................................................... 3 REVISION HISTORY..................................................................................................................................... 5 1 2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
BLOCK DIAGRAM ................................................................................................................................ 7 FUNCTIONAL OVERVIEW.................................................................................................................... 8
INTRODUCTION ................................................................................................................................................................. 8 ATTRIBUTE MEMORY ....................................................................................................................................................... 8 COMMON MEMORY........................................................................................................................................................... 8 I/O SPACE........................................................................................................................................................................... 8 USB HOST CONTROLLER ................................................................................................................................................ 8 UART INTERFACE ............................................................................................................................................................. 9 EEPROM ............................................................................................................................................................................. 9 SOFTWARE DRIVERS ....................................................................................................................................................... 9
3 4
4.1 4.1.1 4.1.2 4.2 4.3
PIN INFORMATION ............................................................................................................................. 10 PIN DESCRIPTIONS............................................................................................................................ 11
POWER SUPPLY FILTERING.......................................................................................................................................... 13 PLL SUPPLY DE-COUPLING....................................................................................................................................... 13 INTERNAL VOLTAGE REGULATOR SUPPLY DE-COUPLING .................................................................................. 14 OSCILLATOR SPECIFICATION....................................................................................................................................... 14 I/O PINS FOR EEPROM DIRECT ACCESS PROGRAMMING MODE ............................................................................ 14 MODE SELECTION .......................................................................................................................................................... 15 NORMAL MODE ........................................................................................................................................................... 15 GENERIC MODE .......................................................................................................................................................... 15 16-BIT PC CARD & COMPACTFLASH/CF+ OPERATION ............................................................................................. 15
5
5.1 5.1.1 5.1.2 5.2
CONFIGURATION & OPERATION ..................................................................................................... 15
6
6.1 6.2 6.3 6.3.1 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.7 6.7.1 6.7.2 6.7.3 6.7.4
PC CARD & COMPACTFLASH/CF+ TARGET CONTROLLER ......................................................... 16
OPERATION ..................................................................................................................................................................... 16 OXCFU950 MEMORY SPACE MAP................................................................................................................................. 16 FUNCTION ACCESS ........................................................................................................................................................ 17 I/O ACCESS WINDOWS............................................................................................................................................... 17 I/O SPACE REGISTER MAP ............................................................................................................................................ 17 I/O SPACE REGISTERS................................................................................................................................................... 18 PC CARD/COMPACTFLASH INTERRUPT...................................................................................................................... 21 INTERRUPT GENERATION ......................................................................................................................................... 21 INTERRUPT SOURCES ............................................................................................................................................... 21 MIO INTERRUPTS........................................................................................................................................................ 22 UART INTERRUPTS..................................................................................................................................................... 22 USB INTERRUPTS ....................................................................................................................................................... 22 UART/USB TEST INTERRUPTS ................................................................................................................................. 22 CONFIGURATION & STATUS REGISTER INTERRUPT REQUEST/ACKNOWLEDGE............................................. 22 PC CARD/COMPACTFLASH FUNCTION CONFIGURATION REGISTERS................................................................... 23 CONFIGURATION OPTIONS REGISTER--COR (OFFSET 0X00) ............................................................................. 23 CONFIGURATION STATUS REGISTER--CSR (OFFSET 0X02) ............................................................................... 24 PIN REPLACEMENT REGISTER--PRR (OFFSET 0X04)........................................................................................... 25 SOCKET & COPY REGISTER--SCR (OFFSET 0X06) ............................................................................................... 25 External--Free Release
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6.7.5 6.8 6.8.1 6.8.2 6.8.3 6.8.4
OXCFU950 DATA SHEET
I/O BASE ADDRESS REGISTER--IOBA (OFFSET 0X0A & 0X0C) ............................................................................ 26 CARD INFORMATION STRUCTURE............................................................................................................................... 26 FIXED DEFAULT CIS IMAGE....................................................................................................................................... 26 STANDARD PRE-PROGRAMMED CIS IMAGE........................................................................................................... 29 EXAMPLE USB SINGLE FUNCTION CIS IMAGE........................................................................................................ 31 EXAMPLE UART SINGLE FUNCTION CIS IMAGE ..................................................................................................... 33
7
7.1 7.2 7.3 7.4 7.5 7.6
USB HOST CONTROLLER ................................................................................................................. 35
WRITING TO AN OHCI REGISTER IN THE EMBEDDED USB HOST CONTROLLER.................................................. 37 READING FROM AN OHCI REGISTER IN THE EMBEDDED USB HOST CONTROLLER ........................................... 37 WRITING TO THE USB MEMORY ................................................................................................................................... 37 READING FROM USB MEMORY..................................................................................................................................... 38 ACCESSING USB MEMORY VIA COMMON MEMORY ACCESS.................................................................................. 38 USB HOST CONTROLLER OVERVIEW.......................................................................................................................... 38
8
UART INTERFACE.............................................................................................................................. 39
MODE SELECTION .......................................................................................................................................................... 39 450 MODE..................................................................................................................................................................... 39 550 MODE..................................................................................................................................................................... 39 750 MODE..................................................................................................................................................................... 39 650 MODE..................................................................................................................................................................... 39 950 MODE..................................................................................................................................................................... 40 REGISTER DESCRIPTION TABLES ............................................................................................................................... 41 RESET CONFIGURATION ............................................................................................................................................... 45 HOST RESET ............................................................................................................................................................... 45 SOFTWARE RESET ..................................................................................................................................................... 45 TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 45 4-BYTE ACCESS TO THR & RHR ............................................................................................................................... 45 FIFO CONTROL REGISTER--FICR ............................................................................................................................ 46 LINE CONTROL & STATUS............................................................................................................................................. 47 FALSE START BIT DETECTION.................................................................................................................................. 47 LINE CONTROL REGISTER--LCR.............................................................................................................................. 47 LINE STATUS REGISTER--LSR ................................................................................................................................. 48 UART INTERRUPTS......................................................................................................................................................... 49 INTERRUPT ENABLE REGISTER--IER...................................................................................................................... 49 INTERRUPT STATUS REGISTER--ISR...................................................................................................................... 50 INTERRUPT DESCRIPTION ........................................................................................................................................ 50 UART POWER SAVING ............................................................................................................................................... 51 MODEM INTERFACE ....................................................................................................................................................... 51 MODEM CONTROL REGISTER--MCR....................................................................................................................... 51 MODEM STATUS REGISTER--MSR .......................................................................................................................... 52 OTHER STANDARD REGISTERS ................................................................................................................................... 52 DIVISOR LATCH REGISTERS--DLL & DLM............................................................................................................... 52 SCRATCH PAD REGISTER--SPR .............................................................................................................................. 52 AUTOMATIC FLOW CONTROL....................................................................................................................................... 53 ENHANCED FEATURES REGISTER--EFR................................................................................................................ 53 SPECIAL CHARACTER DETECTION .......................................................................................................................... 54 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 54 AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 54 BAUD RATE GENERATION............................................................................................................................................. 55 GENERAL OPERATION ............................................................................................................................................... 55 CLOCK PRESCALER REGISTER--CPR..................................................................................................................... 55 TIMES CLOCK REGISTER--TCR................................................................................................................................ 55 ALTERNATIVE BAUD RATE CONTROL REGISTERS................................................................................................ 56 ADDITIONAL FEATURES ................................................................................................................................................ 57 ADDITIONAL STATUS REGISTER--ASR ................................................................................................................... 57 FIFO FILL LEVELS--TFL & RFL .................................................................................................................................. 57 External--Free Release
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8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.5 8.5.1 8.5.2 8.5.3 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.7.1 8.7.2 8.8 8.8.1 8.8.2 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.11 8.11.1 8.11.2
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8.11.3 8.11.4 8.11.5 8.11.6 8.11.7 8.11.8 8.11.9 8.11.10 8.11.11 8.11.12 8.11.13 8.11.14 A_TCR 8.11.15
OXCFU950 DATA SHEET
ADDITIONAL CONTROL REGISTER--ACR................................................................................................................ 57 TRANSMITTER TRIGGER LEVEL--TTL ..................................................................................................................... 58 RECEIVER INTERRUPT. TRIGGER LEVEL--RTL ..................................................................................................... 59 FLOW CONTROL LEVELS--FCL & FCH..................................................................................................................... 59 DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 59 NINE-BIT MODE REGISTER--NMR ............................................................................................................................ 59 MODEM DISABLE MASK--MDM ................................................................................................................................. 60 READABLE FICR--RFC............................................................................................................................................... 60 GOOD-DATA STATUS REGISTER--GDS................................................................................................................... 61 DMA STATUS REGISTER--DMS ................................................................................................................................ 61 PORT INDEX REGISTER--PIX.................................................................................................................................... 61 ALTERNATIVE UART BAUD RATE CONTROL REGISTERS: A_LATCH, A_ENABLE, A_DLL, A_DLM, A_CPR, 61 ALTERNATIVE 32-BIT FIFO ACCESS ENABLE: DBURST ..................................................................................... 61
9 10
10.1 10.2 10.3 10.4
MULTI PURPOSE I/O (MIO) AND USB POWER MANAGEMENT MODULE ..................................... 62 INTERNAL EEPROM SPECIFICATION........................................................................................... 62
ZONE 0 : ZONE HEADER ................................................................................................................................................ 63 ZONE 1 : CIS CONFIGURATION ZONE .......................................................................................................................... 63 ZONE 2 : USB FUNCTION ACCESS ZONE. ................................................................................................................... 64 ZONE 3 : UART FUNCTION ACCESS ............................................................................................................................. 64
11 12 13 14
14.1 14.2 13.1
INTRODUCTION TO THE OXCFU950 SOFTWARE DRIVERS....................................................... 65 OPERATING CONDITIONS ............................................................................................................. 66 DC ELECTRICAL CHARACTERISTICS.......................................................................................... 67 TIMING WAVEFORMS / AC CHARACTERISTICS ......................................................................... 68
MEMORY ACCESS........................................................................................................................................................... 68 I/O ACCESS ...................................................................................................................................................................... 69 2.85 V TO 3.6 V OPERATION........................................................................................................................................... 67
15
15.1
PACKAGE INFORMATION.............................................................................................................. 71
PACKAGE DIMENSIONS ................................................................................................................................................. 72
16
ORDERING INFORMATION ............................................................................................................ 72
NOTES ........................................................................................................................................................ 73 CONTACT DETAILS................................................................................................................................... 74 DISCLAIMER .............................................................................................................................................. 74
REVISION HISTORY
REV Dec 2005 May 2006 Feb 2007 DATE 7 Dec 2005 5 May 2006 REASON FOR CHANGE / SUMMARY OF CHANGE First publication Features revision Updates to reset values for UART Interrupt Enable register (address of 0x15) & Soft Reset and Clock Enable register (address of 0x18); reset text correction for ICR REV register; clarification of use of theOXCFU950 with USB hub devices
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OXCFU950 DATA SHEET
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OXCFU950 DATA SHEET
1
BLOCK DIAGRAM
A[10:0] D[15:0] CE[2:1]# REG# OE# WE# IREQ# IORD# IOWR# RESET PC Card Interface & Control
SOUT CIS & Configuration Registers UART SIN RTS# DTR# CTS# DSR# DCD# RI#
STSCHG#
Internal Data/Control Bus
IOIS16#
Interrupt Logic
XTLI PLL XTLO Clock & Baudrate Generator
MIO pins
MIO[3:0]
128-byte EEPROM USB_DP USB Controller USB PHY USB_DM USB_OTHER
Figure 1: OXCFU950 Block Diagram
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OXCFU950 DATA SHEET
2
2.1
FUNCTIONAL OVERVIEW
Introduction
Traditional OHCI host controllers use memory on the host system, which is not possible for a CompactFlash card, so the OXCFU950 provides 8 Kbytes of on-board RAM for this purpose, which can be accessed via the common memory space and is large enough to contain all the required structures.
The OXCFU950 provides a multi-function CompactFlash interface to a USB 1.1 FS host controller and UART interface. Figure 1 shows the structure of the device. The OXCFU950 provides two functions: USB and UART; and three spaces: attribute memory, common memory and I/O space. It can also be configured, with software support, as a single-function CompactFlash card, supporting either USB-only or UART-only operation. Note: the hardware underpinning both functions is accessible via singlefunction mode, which would facilitate a single-function hybrid driver able to control both the USB and UART functions, if required.
2.4
I/O Space
The I/O space in the OXCFU950 contains three register sets that allow access to local configuration registers (LCRs), USB registers and UART registers. The registers become available when the functions are enabled (via the FCRs). The LCRs provide access to the OXCFU950 non-USB and non-UART functions. They also provide a mechanism to start and stop clocks within the device and to generate a soft reset to the USB controller and UART controller. The UART register set is compatible with the 950, but has been extended to allow higher performance with many host controllers. The USB register set provides indirect 32-bit access to both an OHCI-compatible register set and the common memory space.
2.2
Attribute Memory
The attribute memory space contains the card information structure (CIS) (see PCMCIA metaformat specification), and a set of function configuration registers (FCRs) (see PCMCIA electrical specification) for each function (USB and UART). A CompactFlash host initially reads the CIS from the attribute memory to establish the features and requirements of the OXCFU950. The OXCFU950 provides a default hardwired version of the CIS and a userprogrammable version of the CIS in EEPROM; see Section 5 for details. The CIS is read-only, but programming the internal EEPROM can change its contents. This allows the OXCFU950 to be used in many different applications and allows product differentiation. Each function must be configured and enabled by the host by accessing the appropriate FCRs, which exist at a specific location in attribute memory. The CIS tells the host where the FCRs for each function can be found.
2.5
USB Host Controller
The USB host controller is based on an embedded OHCI model. It provides a single USB 2.0 full-speed (FS) port. A device driver is required on the host PC to access the port, because the OHCI registers must be accessed indirectly, due to limitations of the CompactFlash/CF+ and PCMCIA 16-bit PC Card standards. It is possible to create a device driver that will allow a specific USB device to be accessed via the CompactFlash interface. This could, for example, be used in a product without a public USB interface, where a known USB peripheral is always present. It is also possible to create a device driver that is integrated into the USB stack of the host operating system USB stack. This is ideal for a solution that includes a public USB interface, or for a solution that interfaces into a USB peripheral with existing drivers that could be used with the OS USB stack. Note: The USB controller supports all OHCI endpoint types. However, support is not provided for USB hub devices.
2.3
Common Memory
The USB host controller used in the OXCFU950 is based on the OHCI standard, which defines how the OS and USB host controller communicate. OHCI host controllers use an area of memory and a standard register set. Structures that describe packets that are to be transmitted or have been received are built up in memory, and are read or written by the USB host controller or operating system (OS).
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OXCFU950 DATA SHEET
2.6
UART Interface
section 4.3. The functional use of the EEPROM is discussed in section 10.
2.8
Software Drivers
The UART interface provides a 550- and 950-compatible register set, with all the usual 950 features. It has also been extended over the normal 950 register set to include a number of performance-enhancing features. The UART is completely synchronous with a maximum baud rate of 12 Mbps. The UART clock can be switched off to save power, and it also includes an asynchronous wakeup mechanism.
The OXCFU950 USB host controller is typically driven by the appropriate Oxford Semiconductor supplied driver. The UART interface can be driven either by an appropriate Oxford Semiconductor serial driver or by the default serial driver of the operating system. The advanced features of the UART interface are not available to default drivers. See section 11 for further information.
2.7
EEPROM
The OXCFU950 contains an integral 8-Kbyte EEPROM, which is used to hold user-configurable CIS and LCR (local configuration register) data. The EEPROM can be configured using Oxford Semiconductor software utilities via a host machine or during board manufacture; see
.
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OXCFU950 DATA SHEET
3
PIN INFORMATION
Figure 2: OXCFU950 Pin Information (QFN64)
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OXCFU950 DATA SHEET
4
PIN DESCRIPTIONS
Description PC Card/CompactFlash address bus, bits [10:0] PC Card/CompactFlash data bidirectional bus. Register select and I/O enable. Active-low card enable. Active-low output enable used to gate memory read data (attribute memory). Host must negate the OE# signal during write operations. Active-low write enable used for strobing memory write data (attribute memory). Active-low I/O read enable. Active-low I/O write enable. Write protect (in memory-only mode). Data is 16-bit (in I/O & memory mode). PC Card/CompactFlash reset. Note : This pin requires an external reset pulse generator (RC network) to allow for the startup time for the internal oscillator and PLL. Device ready (in memory-only mode). Active-low Interrupt request (in I/O & memory mode). Indicates to the host system that the PC Card/CF requires host software service. Note: interrupt can support level or pulsed types. Battery voltage detect 1 (in memory-only mode). Not supported so held static. Active-low status-changed pin (in memory & I/O mode). Used to alert the host system that the card status has changed. In this case it means that a function's ready state has changed. The host should check this by considering each function's PRR. Connected internally. UART serial data output. UART IrDA data output when MCR[6] set in enhanced mode. UART serial data input. UART IrDA data input when IrDA mode is enabled (see above). Active-low modem data-carrier-detect input. Active-low modem data-terminal-ready output. If automated DTR# flow control is enabled, the DTR# pin is asserted & deasserted if the receiver FIFO reaches or falls below the programmed thresholds. In RS485 half-duplex mode, the DTR# pin may be programmed to reflect the state of the transmitter empty bit to control the direction of the RS485 transceiver buffer automatically (see register ACR[4:3]). Active-low modem request-to-send output. If automated RTS# flow control is enabled, the RTS# pin is de-asserted & reasserted when the receiver FIFO reaches or falls below the programmed thresholds. Active-low modem clear-to-send input. If automated CTS# flow control is enabled, upon de-assertion of the CTS# pin the transmitter completes the current character & enters idle mode until the CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. Active-low modem data-set-ready input. If automated DSR# flow control
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Pin Number Pad TypeNote 1 Pin Name PC Card/Compact Flash Interface & ControlNote 2 14,16,17,18,21,22,23, I_C_33_5_N_ A[10:0] 25,29,31, 34 13,11,9,46,44,42,40,38 B_T_33_5_N_2_ D[15:0] ,10,8,6,45,43,41,39,37 15 I_C_33_5_N_ REG# 35,36 I_C_33_5_N_ CE[2:1]# 33 I_C_33_5_N_ OE# 26 32 30 7 19 24 I_C_33_5_N_ I_C_33_5_N_ I_C_33_5_N_ O_T_33_1 I_C_33_5_S_ O_T_33_2 WE# IORD# IOWR# WP IOIS16# RESET READY IREQ# 12 O_T_33_2 BVD1 STSCHG#
5,28,47 P_33 UART (MODEM) FunctionNote3 58 O_T_33_1 53 56 60 I_C_33_5_N_ I_C_33_5_N_ O_T_33_1
PCMCIA_VDD3V3 SOUT IrDA_Out SIN IrDA_In DCD# DTR#
485_En 59 54 O_T_33_1 I_C_33_5_N_ RTS# CTS#
55
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Pin Number Pad TypeNote 1 Pin Name
OXCFU950 DATA SHEET
57 1
I_C_33_5_N_ P_33
RI# UART_VDD3V3 XTLO XTLI PLL_VSS1V8 PLL_VDD1V8 USB_DP USB_DM USB_VDD3V3 MIO[3:0]
Description is enabled, upon de-assertion of the DSR# pin, the transmitter completes the current character & enters idle mode until the DSR# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the DSR# pin. Active-low modem ring-indicator input. Power supply to UART and MIO I/O interfaces. Voltage on these pins should be tied to 1.8 V to 3.3 V supply (depending on requirement). Crystal oscillator output. Crystal oscillator input. Frequency = 12 MHz. Note : a pull-down resistor of 500 K is required on this pin. Ground (0 Volts) for PLL & oscillator cells. This pin should be tied to ground. Power supply for PLL & oscillator cells. This pin should be tied to 1.8 volts (i.e. tied to REG_VDD1V8 pin). USB data plus. USB data minus. Power supply to USB I/O interface. This pin should be tied to 3.3 volts. Multipurpose IO pins. Note: if enabled, MIO[3:0] can be used as an interrupt inputs. MIO[3:2] can be configured to act as the USB power management control signals PORT_OVER_CURRENT & PORT_POWER Test mode select pin/default CIS select. (See Section 5.1) Test pin. This pin should be tied to VSS for normal operation. Main digital ground pin. The VSS pin should be tied to ground. Note this is the thermal bonding pin underneath the 64-pin QFN package Output supply from internal voltage regulator at 1.8 V. Can be used as power supply to PLL (i.e. pin #48).
Crystal Oscillator / PLL pinsNote4 51 A_18 50 A_18 49 48 USBNote 5 2 3 4 Multi-Purpose I/ONote 3 64,63,62,61 P_18 P_18 A_33 A_33 P_33 B_T_33_5_N_1_
Miscellaneous Pins/PadsNote2 52 I_C_33_5_N_U 20 I_C_33_5_N_D Additional Power and Ground 65 (Thermal bonding P_00 pad) 27 P_18
CIS_MODE TEST VSS REG_VDD1V8
Table 1: Pin Descriptions Note 1 : Pad syntax description
Pad type Digital Input pad Digital Output pad Digital Tristate output pad Digital Bidirectional pad Analogue pad Power Pad syntax t_a_xy_h_i_p t_a_xy_d t_a_xy_d t_a_xy_h_i_d_p t_xy t_xy
Table 2: Pad Type Syntax
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symbol t description Pad type values I--input pad O--output pad T--Tri-state output pad B--Bidirectional pad A--Analogue pad P--Power pad C--cmos T--TTL 33--3V3 18--1V8 00--0 V (i.e. VSS Ground) 5--5 V N--same as operating voltage N--normal S--Schmitt 1--x1 drive strength 2--x2 drive strength 3--x3 drive strength U--pull up resistor D--pull down resistor
OXCFU950 DATA SHEET
a xy h i d p
Logic type Operating voltage Tolerant input voltage level Input type Output drive strength Pull up/down resistor
Table 3: Pad Type Syntax Symbol Descriptions Note 2 : PC Card/CompactFlash Power Domain Group * This group of signals is in the PC Card/CompactFlash power domain group. * Supply voltage range is specified from 2.85 V to 3.6 V. * This is also the internally connected supply to the internal regulator. Hence pin #28 should be connected to the PC Card/CompactFlash supply source. Note 3 : Modem Power Domain Group * This group of I/O signals is in the MODEM power domain group. * Supply voltage range is specified from 1.8 V to 3.6 V. Note 4 : Analogue Power Domain Group * This group of I/O signals is in the analogue power domain group (which supplies the oscillator and PLL). Note 5 : USB Power Domain Group * This group signals is in the USB power domain group. * Supply voltage range is specified from 2.85 V to 3.6 V.
4.1
4.1.1
Power Supply Filtering
PLL Supply De-Coupling
The low frequency noise at the Vdd and Gnd supplies is automatically corrected by the PLL control loop. However, where noise frequency exceeds the loop bandwidth (60 to 100kHz) the noise is partially converted into clock jitter. The conversion of supply noise into long-term clock jitter is important above 700 kHz. Oxford Semiconductor recommends you to filter Vdd in this range efficiently. For full-speed USB applications, where the jitter must not exceed 0.5 ns peak for a time duration approximately 1.2 s, Oxford Semiconductor recommends you to ensure that the noise level above 700kHz is lower than 7mV rms.
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OXCFU950 DATA SHEET
4.1.2
Internal Voltage Regulator Supply De-Coupling
Adequate output supply decoupling is mandatory to reduce ripple and avoid oscillations--use two capacitors in parallel on the REG_1V8 pin: * One external 470-pF (or 1-nF) NPO capacitor must be connected between REG_VDD1V8 (pin #27) & VSS as close to the chip as possible * One external 2.2-F (or 3.3- F) X7R capacitor must be connected between REG_VDD1V8 (pin #27) & VSS as close to the chip as possible Note : Z5u and Y5V capacitors must be avoided--the poor high-frequency behavior of these dielectrics makes them unsuitable for power supply decoupling. Adequate input supply decoupling is mandatory to improve start-up stability and reduce source voltage drop_ * One external 100-pF NPO capacitor must be connected between REG_VDDV3V (pin #28) & VSS as close to the chip as possible * One external 4.7- F X7R capacitor must be connected between REG_VDD3V3 (pin #28) & VSS as close to the chip as possible
4.2
Code Ton Pon ESR Cm Cshunt Cload
Oscillator Specification
Parameter Startup Time Drive level Equivalent series resistance Motion capacitance Shunt capacitance Load Capacitance Condition With crystal defined below Min Typ Max 2 150 80 9 7 20 Unit ms W Ohm fF pF pF
5 Max external capacitors: 40 pF 15
XTLI and XTLO shall not be used to drive other circuits. The external capacitors on XTLI and XTLO must have the correct crystal load capacitance (max 40 pF). Additionally, a 500-K pull-down resistor is required on XTLI.
4.3
I/O Pins for EEPROM Direct Access Programming Mode
The OXCFU950 allows a direct access mode to the internal EEPROM, for programming the EEPROM without using the PC Card Interface. This can be used by manufacturers to configure The EEPROM during board manufacture. The following table shows the pins used for this EEPROM programming mode. Pin Name TEST A6 A5 A4 A8 A9 READY Z_IORD A7 Z_WE Z_IOWR Direction Input Input Input Input Input Input Output Input Input Input Input Pin Usage Description Test mode enable signal (Set to `logic 1' - VDD3V3) Static test signal (set to logic `1' - VDD3V3) Static test signal (set to`logic `1' - VDD3V3) Static test signal (set to logic `0' - VSS) Serial data in (SDI) Shift & load Serial data out (SDO) Test clock input Write-enable signal to write in the memory (active-low) Reset signal EEPROM test-enable signal
Full details of the internal configuration of the EEPROM and details of programming utilities are available on request from Oxford Semiconductor.
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5
5.1
CONFIGURATION & OPERATION
Mode Selection
The host system then loads the device-driver software according to the tuple information and configures the I/O, memory and interrupt resources. After determining that the device is a memory and I/O type device, the host enables its I/O mode by writing to its configuration options register(s) in attribute memory space. Device drivers can then access the functions at the assigned addresses. A set of LCRs is provided to control the device characteristics, such as interrupt handling, and report its internal functional status. Two zones in the EEPROM can be used to redefine the reset values of all the registers in I/O space. One zone is executed when the USB function is reset; the other is executed when the UART is reset. In this way the USB and UART functions can be tailored to end-user requirements if the default values do not meet the specific requirements of the manufacturer. It is good practice to make sure that the EEPROM is always used to provide reset values for the LCR registers. Because each function can access any of the LCR registers, using the EEPROM in this way gives ownership of each LCR to a specific function. This feature can also be used to pre-configure the USB or UART registers without modifying the device driver. This allows, for example, the enhanced features of the integrated UART to be in place prior to handing over to any generic device drivers. It is also possible to pre-configure and then lock four of the UART registers (CPR, TCR, DLL, DLM), so they cannot be modified by the device driver. Device reprogramming can also be performed for the CIS area, for example to allow the manufacturer to modify the resources required or manufacturer ID values. Note: a default set of tuples is provided for both multifunction and single-function solutions.
The OXCFU950 has two modes of operation, as shown in the table below.
CIS_MODE pin 1 0 Operation Normal mode Generic mode
Table 4: Modes of Operation
5.1.1
Normal Mode
The chip usually operates in normal mode, in which the contents of the EEPROM are used to define the CIS and the action taken on a USB/UART reset. If no CIS is found in the EEPROM, the hard-wired CIS is used.
5.1.2
Generic Mode
Generic mode disables the EEPROM controller. It forces the OXCFU950 to use the hardwired CIS. Under normal circumstances it should not be used unless an image placed on the EEPROM provides an invalid CIS. In this event, it is unlikely that the OXCFU950 can be enumerated in normal mode, so the contents of the EEPROM can only be changed by using generic mode.
5.2
16-Bit PC Card & CompactFlash/CF+ Operation
PCMCIA 16-bit PC Card and CompactFlash/CF+ host systems allow for hot card insertion. When a card is inserted into a host system, the host system configures it. The PCMCIA standard defines two card detect pins that allow the host to be notified when a card is inserted or removed. By default the device powers up in either normal or generic mode, depending on the CIS_MODE pin. The host system waits for the READY# signal to be active before reading the CIS in the attribute memory of the device. By reading this tuple information, the host system is able to identify the device type and the necessary resources requested by the device.
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6
6.1
PC CARD & COMPACTFLASH/CF+ TARGET CONTROLLER
Operation
Note: See section 14 for timing waveforms. The OXCFU950 responds to a number of different 16-bit PC Card/CompactFlash accesses (detailed below). Section 14 contains timing diagrams and information for each of these types of access: * * * Direct common memory read/writes: These are required to gain access to the 8 Kbytes of RAM used by the OHCI USB host controller. Direct attribute memory read/writes: Access to direct attribute memory is required to allow the host access to both the CIS and FCRs (for each function). Valid data is 8 bits wide and on even bytes only, for direct attribute memory. I/O read/writes: I/O accesses are performed to access the USB host controller, UART and local configuration registers. Data width is restricted to 8 bits, as required by the standard UART function. While the device CIS information configures the card as a multifunction device, the host (or device driver/EEPROM controller) must set up a base address within I/O space for each function. As reads and writes are immediate, there is no requirement to hold the WAIT# signal in its active state, thus providing maximum speed access to I/O space.
6.2
OXCFU950 Memory Space Map
Attribute Memory Common Memory
USB host RAM Function 1 - Function Configuration Registers (Base Address 0x300) The actual RAM is 8 Kbytes in size. This area of memory is only 2 Kbytes in size (a limitation of the size of the Compact Flash address bus). A paging mechanism is therefore used to allow access to the full 8 Kbytes Function 0 I/O Window Up to 64 bytes of I/O space. Can be placed anywhere by host
Host I/O Space
Function 0 - Function Configuration Registers (Base Address 0x200)
Function 1 I/O Window CIS The CIS is programmed from EEPROM and therefore not of a fixed size. It's maximum size is 256 bytes addressable on even locations between 0x000 and 0x1FE Up to 64 bytes of I/O space. Can be placed anywhere by host
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6.3
Function Access
6.3.1
I/O Access Windows
The OXCFU950 can support two functions. Each function has its own I/O access window and each window has a programmable base address and is up to 64 bytes long. The windows can therefore be located anywhere in the host I/O space, and there is no assumed relationship between their positions. The base address for each window can be set either by using the I/O base address register (in attribute memory--see the PCMCIA electrical specification) or by using the alternative I/O base address register set in the I/O space. The register can be set up by the EEPROM on a reset.
6.4
I/O Space Register Map
Function UART UART 32-bit FIFO access Register Standard UART registers
Offset from function's base address in I/O space 0x00 through to 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 through to 0x40
LCRs (EEPROM control) UART Extra Features LCRs
EEPROM status & control register
USB
TEST register. I/O or memory mode function enable Multipurpose I/O configuration register IRQ test register MIO interrupt enable register USB interrupt enable register UART interrupt enable register Interrupt status register Soft USB reset & clock enable register Soft UART reset & clock enable register Soft system reset & clock enable register EEPROM clock control register Alternative I/O base control register Alternative UART I/O base 0 register Alternative UART I/O base 1 register Alternative USB I/O base 0 register Alternative USB I/O base 1 register USB host controller registers
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6.5
0x00 to 0x0B Notes 0x0C Notes Bits 7 6 5 4 3 2 1 0 0x0D to 0x0F Note
I/O Space Registers
UART See Section 8 for details of the UART register map EEPROM Status and Control Register This 8-bit register provides bitmapped access to the control signals of the EEPROM. By manipulating these signals it is possible to program and read back the various locations of the EEPROM. Description Read/Write Reset EEPROM Host Access e2_rdybsyn R X e2_fn_wtn RW 0 e2_fn_shandloadb RW 0 e2_fn_sdi / e2_fn_sdo RW 0 e2_fn_clock RW 0 e2_fn_reset RW 0 e2_fn_test RW 0 e2_valid R X UART See Section 8 for details of the UART register map
0x10 Notes Bits 7:0
Test This register provides 8 bits of read/write storage & can be used for test purposes. Description Test register Bit 1--enables I/O memory mode for UART Bit 3--enables I/O memory mode for USB Read/Write EEPROM Host Access W R/W Reset 10100101
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0x11 Bits 7:6 Multi-Purpose I/O Configuration Register Description MIO3 configuration register 00--MIO3 is a non-inverting input pin 01--MIO3 is an inverting input pin 10--MIO3 is an output pin driving `0' 11--MIO3 is an output pin driving `1' MIO2 configuration register 00--MIO2 is a non-inverting input pin 01--MIO2 is an inverting input pin 10--MIO2 is an output pin driving `0' 11--MIO2 is an output pin driving `1' MIO1 configuration register 00--MIO1 is a non-inverting input pin 01--MIO1 is an inverting input pin 10--MIO1 is an output pin driving `0' 11--MIO1 is an output pin driving `1' MIO0 configuration register 00--MIO0 is a non-inverting input pin 01--MIO0 is an inverting input pin 10--MIO0 is an output pin driving `0' 11--MIO0 is an output pin driving `1' IRQ Test register Description Reserved Function `1' IRQ (USB). When set forces USB IRQ to be generated. Function `0' IRQ (UART). When set forces UART IRQ to be generated. MIO Interrupt Enable Register Description Reserved MIO[3] interrupt enable MIO[2] interrupt enable MIO[1] interrupt enable MIO[0] interrupt enable USB Interrupt Enable Register Description Reserved USB fast IRQ enable USB interrupt enable UART Interrupt Enable Register Description Reserved UART host interrupt enable
OXCFU950 DATA SHEET
Read/Write EEPROM Host Access W R/W
Reset 00
5:4
W
R/W
00
3:2
W
R/W
00
1:0
W
R/W
00
0x12 Bits 7:2 1 0 0x13 Bits 7:4 3 2 1 0 0x14 Bits 7:2 1 0 0x15 Bits 7:1 0
Read/Write EEPROM Host Access R W R/W W R/W
Reset 000000 0 0
Read/Write EEPROM Host Access R W R/W W R/W W R/W W R/W
Reset 0000 0 0 0 0
Read/Write EEPROM Host Access R R/W W R/W
Reset 000000 0 0
Read/Write EEPROM Host Access R W R/W
Reset 0000000 1
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0x16 Bits 7
Interrupt Status Register Description Reserved Read/Write EEPROM Host Access R Reset 0
6 5 4 3 2 1 0 0x17 Bits 7:6 5 4 3 2 1 0 0x18 Bits 7:2 1 0 0x1A Bits 7:1 0 0x1B Bits 7:2 1 0
Read: USB fast IRQ status Write: Setting this bit to `1' clears the USB fast IRQ. This bit reflects the state of the USB interrupt This bit reflects the state of the UART interrupt MIO3. This bit reflects the state of the internal MIO[3] MIO2. This bit reflects the state of the internal MIO[2] MIO1. This bit reflects the state of the internal MIO[1] MIO0. This bit reflects the state of the internal MIO[0] Soft USB Reset & Clock Enable Register Description Reserved 0--selects USB OVER_CURRENT signal is active-high input 1--selects USB OVER_CURRENT signal is active-low input 0--selects normal MIO3 functions 1--selects MIO3 as OVER_CURRENT (input) signal 0--selects USB PORT_POWER signal is active-high output 1--selects USB PORT_POWER signal is active-low output 0--selects normal MIO2 functions 1--selects MIO2 as USB PORT_POWER (output) signal Active-high clock enable for USB host controller Active-high soft reset for USB host controller Soft UART Reset & Clock Enable Register Description Reserved Active high clock enable for UART Active high soft reset for UART EEPROM Clock Control Register Description Reserved EEPROM clock enable Alternate I/O Base Control Register Description Reserved Select alternate I/O base address for USB Select alternate I/O base address for UART External--Free Release
-
R/W R R R R R R
0 0 0 X X X X
Read/Write Host EEPROM W W W W W W R R/W R/W R/W R/W R/W R/W
Reset 00 0 0 0 0 0 0
Access
Read/Write Host EEPROM W W R R/W R/W
Reset 000000 1 0
Access
Read/Write Host EEPROM W R R/W
Reset 0000000 1
Access
Read/Write Host EEPROM W W R R/W R/W
Reset 000000 0 0
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Access
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0x1C Bits 7:0 0x1D Bits 7:3 2:0 0x1E Bits 7:0 0x1F Bits 7:3 2:0 0x20 to 0x40 Notes
Alternate UART I/O Base 0 Register Description Alternate UART I/O base address bits 7:0 Alternate UART I/O Base 1 Register Description Alternate UART I/O base address bits 15:11 Alternate UART I/O base address bits 10:8 Alternate USB I/O Base 0 Register Description Alternate USB I/O base address bits 7:0 Alternate USB I/O Base 1 Register Description Alternate USB I/O base address bits 15:11 Alternate USB I/O base address bits 10:8 USB Host Controller See Section 7 for details of the USB host controller register map. Read/Write EEPROM Host Access R W R/W Reset 00000 000 Read/Write EEPROM Host Access W R/W Reset 00000000 Read/Write EEPROM Host Access R W R/W Reset 00000 000 Read/Write EEPROM Host Access W R/W Reset 00000000
6.6
6.6.1
PC Card/CompactFlash Interrupt
Interrupt Generation
pulse is guaranteed to be greater than the minimum length of 0.5 s as defined in the PCMCIA standard.
PCMCIA 16-bit PC Cards and CompactFlash/CF+ cards support pulse or level type interrupt signals to request interrupt service from the host system. The CIS of the card specifies whether pulse, level or both types of interrupt can be generated. When the host has read the CIS, it can set the LevlReq field in the Configuration Options Register (COR) for each function, to tell the card which type of interrupts should be generated. The OXCFU950 can generate either type of interrupt. However, to reduce power consumption, the default CIS states that only level type interrupts can be generated. A custom CIS can be constructed to direct the card to generate pulse type interrupts if required, by using appropriate EEPROM values. The OXCFU950 uses a clock divider circuit clocked at 12 MHz to generate pulse type interrupts. The generated
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6.6.2
Interrupt Sources
The OXCFU950 has six possible interrupt sources: the UART function, the USB host controller function and the four multi-purpose I/O (MIO) pins, which can be configured as interrupts using the MIO configuration register (MIO [3:0]) and the interrupt status and control register (ISR) The OXCFU950 is a multi-function device with two functions, the UART function (function 0) and the USB host controller function (function 1). Interrupts generated by MIO [3:0] are mapped to UART function 0 so that any MIO enabled interrupt sets the Intr bit to `1' in the UART CSR.
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6.6.3
MIO Interrupts
6.6.7
Intr Field
To enable one or more MIO interrupts, the appropriate bit(s) in the MIO interrupt enable register (an LCR at offset 0x13) must be set to `1' by the host system. Bit 0 corresponds to the MIO[0] interrupt enable, bit 1 corresponds to MIO[1] interrupt enable, bit 2 corresponds to MIO[2] interrupt enable and bit 3 corresponds to MIO[3] interrupt enable. When an MIO interrupt is asserted, the Intr field in the UART CSR is set to `1'
Configuration & Status Register Interrupt Request/Acknowledge
The Intr field (bit 1 of the CSR) reports whether the function is requesting interrupt servicing and may be used to acknowledge that the host system is ready to process another interrupt request from the PC Card. The function sets this field to `1' to request interrupt service. `0' signifies that it is not requesting interrupt service. Writes to the Intr field in the CSR are ignored when the IntrAck field of both CSRs on the PC Card are reset to zero. If the host system writes a `0' to this field in any CSR on the PC Card when the IntAck field of any CSR is set to `1' and either function on the PC Card is requesting interrupt servicing, the PC Card must create an additional interrupt notification to the host system. IntrAck Field The interrupt acknowledge field (IntrAck, bit 0 of the CSR) changes the response characteristics of the Intr field. This field is used to enable a hardware/software protocol that permits the IREQ# signal to be shared by the two functions. If the IntrAck bit for both function CSRs is set to `0', writes to the Intr field are ignored. If the IntAck bit for either function is set to `1': * The host system must acknowledge it is ready to receive additional interrupts from the PC Card by writing `0' to the Intr field of either function CSR after the host system has completed an entire interrupt processing cycle. The PC Card creates an additional interrupt notification to the host system when the host system writes a `0' to the Intr bit to either function CSR and either function on the PC Card enabled for interrupt reporting and sharing is requesting interrupt service.
6.6.4
UART Interrupts
To enable the UART interrupt, set bit 0 (the UART interrupt enable bit in the UART interrupt enable register, which is an LCR register at offset 0x15) to `1'. When a UART interrupt is asserted, the Intr field within the UART CSR is set to `1'.
6.6.5
USB Interrupts
The OXCFU950 supports two forms of USB interrupt: the standard OHCI interrupt (standard IRQ) and a faster interrupt. Oxford Semiconductor USB host driver software uses the faster interrupt (fast IRQ) to improve system performance., USB Standard IRQ To enable the USB interrupt, set bit 0 (the USB Host interrupt enable bit in the USB interrupt enable register, an LCR register at offset 0x14) to `1'. When a USB interrupt is asserted the Intr field within the USB CSR is set to `1'. USB Fast IRQ To enable the fast USB IRQ, set bit 1, the USB host fast enable bit in the USB interrupt enable register (an LCR register at offset 0x14) to `1'.
*
6.6.6
UART/USB Test Interrupts
There is a test facility for the host system to initiate UART and USB interrupts by writing to the UART/USB Interrupt Test Register at offset address 0x12. To force a function 0 UART interrupt, set bit 0 of the UART/USB Interrupt Test Register to `1'. To force a function 1 USB interrupt, set bit 1 of the UART/USB Interrupt Test Register to `1'.
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6.7
PC Card/CompactFlash Function Configuration Registers
Each function supplied by a 16-bit PC Card or CompactFlash/CF+ card must implement function configuration registers (FCRs). These registers allow the host to configure the function provided by the card, and are mapped into the attribute memory space at the location specified within the CONFIG tuple for that function in the CIS. The CONFIG tuple defines a base address for the FCRs and also shows which FCRs are supported by that function. The registers supported in the OXCFU950 are shown in the following table.
Offset from FCR base address 0x00 0x02 0x04 0x06 0x0A 0x0C Attribute memory address (USB) 0x300 0x302 0x304 0x306 0x30A 0x30C Attribute memory address (UART) 0x200 0x202 0x204 0x206 0x20A 0x20C Register Configuration options register Configuration & status register Pin replacement register Socket & copy register I/O base address register 0 I/O base address register 1
Table 5: Configuration Register Mapping The definition of each configuration register is detailed below.
6.7.1
Configuration Options Register--COR (Offset 0x00)
The configuration options register is used to configure 16-bit PC Card and CompactFlash/CF+ cards that have programmable address decoders. When the card client driver has successfully parsed the CIS, it attempts to obtain system resources as requested by the CIS. On completion of this it assigns the resources to the card via the COR. The COR format and description is given in Table 6.
D7 SRESET Field SRESET D6 LevIREQ Type R/W D5 D4 D3 D2 Function Configuration Index D1 D0
LevIREQ1 Function Configuration Index
R/W R/W
Description Software reset Setting this field to `1' places the card in the reset state. This is equivalent to setting the RESET signal (on pin) except this SRESET field is not reset. Returning this field to `0' leaves the card in the same un-configured, reset state as the card would be following a power-up and hard reset. Level Mode IREQ# Setting this field to `1' enables level type interrupts Setting this field to `0' enables pulse type interrupts Configuration Index The host sets this field to the value of the Configuration Entry Number field of a Configuration Table Entry tuple as defined in the CIS. On setting the non-zero value in this field the function IO is enabled and IO accesses are allowed. When the field is set to zero (e.g. after a hard reset) the card will be configured to memory only mode and all IO accesses will be ignored by the card.
Table 6: Configuration Option Register Note 1 The default tuples in the CIS tell the host that only level type interrupts are supported, to allow lowest power consumption. The OXCFU950 supports both level and pulse type interrupts, and if a particular manufacturer requires to use pulse type, or both, then the CIS can be modified using the internal EEPROM.
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6.7.2
Configuration Status Register--CSR (Offset 0x02)
The configuration and status register is an optional register supported by the OXCFU950. The register allows additional control over function configuration and reports the configuration status.
D7 Changed Field Changed Type R D6 SigChg D5 IOIs8 D4 RFU D3 Audio D2 PwrDwn D1 Intr D0 IntrAck
Description If a 16-bit PC Card or CompactFlash/CF+ card is using the I/O interface, the pin replacement register for the function is present & one or more of the state change signals in the pin replacement register are set to 1, or one of the Event bits in the extended status register is 1 and the corresponding Enable bit is 1, the function sets this field to 1. If a 16-bit PC Card or CompactFlash/CF+ card is not using the I/O interface or the pin replacement register for the function is not present, this field is undefined and should be ignored. This field serves as a gate for STSCHG# If a 16-bit PC Card or CompactFlash/CF+ card is using the I/O interface & both the Changed and SigChg fields are set to 1, the function asserts STSCHG#. If a 16-bit PC Card or CompactFlash/CF+ card is using the I/O interface and this field is reset to 0, the function does not assert STSCHG#. If a 16-bit PC Card or CompactFlash/CF+ card is not using the I/O interface or the pin replacement register for the function is not present, this field is undefined and should be ignored. The host sets this field to 1 when it can provide I/O cycles only with an 8-bit D[7..0] data path. The card is guaranteed that accesses to the 16-bit registers will occur as two byte accesses rather than as a single 16-bit access. Reserved. Must be 0. This bit is set to 1 to enable audio information on SPKR# when the card is configured. Not used: 0 When the host sets this field to 1, the function enters a power-down state, if such a state exists. Not used: 0 If a 16-bit PC Card or CompactFlash/CF+ card function does not have a power-down state, the function ignores this field. Interrupt request/acknowledge - This field reports whether the function is requesting interrupt servicing and may be used to acknowledge the host system is ready to process another interrupt request from the 16-bit PC Card or CompactFlash/CF+ card. The function shall set this field to 1 when it is requesting interrupt service. The function sets this field to 0 when it is not requesting interrupt service. Writes to this field are ignored when the IntrAck field of all configuration and status registers on the 16-bit PC Card or CompactFlash/CF+ card are reset to 0. Single function cards ignore this field on writes and always return 0.
SigChg
R/W
IOIs8 RFU Audio1 PwdDwn2
R/W R/W R/W
Intr
R
IntrAck
R/W
Table 7: Configuration Status Register Note 1 Audio is not supported on the device. Note 2 The OXCFU950 does not support a specific power-down mode, because it is a low power device that features a number of sleep modes (see Section 6.7 for further details).
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6.7.3
Pin Replacement Register--PRR (Offset 0x04)
The pin replacement register is implemented to provide information about READY, WP or the BVD[2..1] status when implementing the I/O interface.
D7 CBVD1 Field CBVD1 CBVD2 CREADY CWProt RBVD1 D6 CBVD2 D5 CREADY D4 CWProt D3 RBVD1 D2 RBVD2 D1 RREADY D0 RWProt
Description This bit is set (1) when the corresponding bit, RBVD1, changes state. This bit may also be written by the host. Not used: 0 This bit is set (1) when the corresponding bit, RBVD2, changes state. This bit may also be written by the host. Not used: 0 This bit is set (1) when the corresponding bit, RREADY, changes state. This bit may also be written by the host. This bit is set (1) when the corresponding bit, RWProt, changes state. This bit may also be written by the host. Not used: 0 When read, this bit represents the internal state of the Battery Voltage Detect circuits on the BVD1 pin. Not used: 1 When this bit is written as 1 the corresponding CBVD1 bit is also written. When this bit is written as 0, the CBVD1 bit is unaffected. When read, this bit represents the internal state of the Battery Voltage Detect circuits on the BVD2 pin. Not used: 1 When this bit is written as 1 the corresponding CBVD2 bit is also written. When this bit is written as 0, the CBVD2 bit is unaffected. When read, this bit represents the internal state of the READY signal. This bit may also be used to determine the state of READY as that pin has been relocated for use as Interrupt Request on IO Cards. When this bit is written as 1 the corresponding changed bit is also written. When this bit is written as 0, the changed bit is unaffected. When read, this bit represents the state of the WP signal. This signal may also be used to determine the state of the Write Protect switch when pin 33 is being used for IOIS16#. Not used: 0 When this bit is written as 1 the corresponding changed bit is also written. When this bit is written as 0, the changed bit is unaffected.
RBVD2
RREADY
RWProt
Table 8: Pin Replacement Register
6.7.4
Socket & Copy Register--SCR (Offset 0x06)
This is an optional read/write register implemented by the OXCFU950, which the 16-bit PC Card or CompactFlash/CF+ card may use to distinguish between similar cards installed in a system. This register is always written by the system before writing the card Function Configuration Index field in the COR.
D7 Reserved Field Reserved Copy Number D6 D5 Copy Number D4 D3 D2 D1 Socket Number D0
Description This bit is reserved for future standardization. This bit must be set to zero (0) by software when the register is written. 16-bit PC Card and CompactFlash/CF+ cards that indicate in their CIS that they support more than one copy of identically configured cards, should have a copy number (0 to MAX twin cards, MAX = n-1) written back to the SCR. This field indicates to the card that it is the n'th copy of the card installed in the system, which is identically configured. The first card installed receives the value 0. This permits identical cards designed to share a common set of I/O ports while remaining uniquely identifiable and consecutively ordered. This field indicates to the 16-bit PC Card and CompactFlash/CF+ card that it is located in the n'th socket. The first socket is numbered 0. This permits any cards designed to do so to share a common set of I/O ports while remaining uniquely identifiable.
Socket Number
Table 9: Socket and Copy Register
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6.7.5
I/O Base Address Register--IOBA (Offset 0x0A & 0x0C)
This register holds the I/O base address that the host PC has assigned this function.
D7 D6 D5 D4 D3 IO Base Address (7:0) D2 D1 D0
Field IO Base Address (7:0)
Description Bits 7:0 of I/O base address for function.
Table 10: IOBA 0 (Offset 0x0A)
D7 Field IO Base Address (7:0) D6 Reserved Description Bits 7:0 of I/O base address for function. D5 D4 D3 D2 D1 D0 Bits 10:8 of I/O base address
Table 11: IOBA 1 (Offset 0x0C)
6.8
Card Information Structure
The card information structure (CIS) in the OXCFU950 is normally sourced from the integral EEPROM, and the OXCFU950 is usually shipped with a standard pre-programmed CIS image, which is documented in Section 6.8.2. When the EEPROM image is invalid, or when the CIS_Mode pin is asserted, the CIS defaults to a fixed default CIS image, which is documented in Section 6.8.1. Both the default CIS Image and the standard pre-programmed CIS image support multi-function operation.
6.8.1
Fixed Default CIS Image
Description Common Memory: 1) SRAM 2) 200 ns 3) 1x2048 bytes Attribute Memory: 1) ROM 2) 200 ns 3) 1x512 bytes (CIS) 4) 1x512 bytes (Registers) Common Memory at 3.3 volts
Value (Hex) Tuple Name Direct Attribute (Offset 0x0000) 01 CISTPL_DEVICE 03 62 01 FF 17 CISTPL_DEVICE_A 05 12 00 D2 00 FF 1C CISTPL_DEVICE_OC 04 03 62 01 FF 1D CISTPL_DEVICE_OA 06 03 12 00 D2 00 FF
Attribute Memory at 3.3 volts
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Value (Hex) Tuple Name 06 CISTPL_LONGLINK_MFC 0B 02 00 50 00 00 00 00 A0 00 00 00 20 CISTPL_MANFID 04 79 02 2A 95 15 CISTPL_VERS_1 15 06 01 43 46 20 43 41 52 44 00 47 45 4E 45 52 49 43 00 00 00 FF FF CISTPL_END Direct Attribute (Offset 0x00A0) 13 CISTPL_LINKTARGET 03 43 49 53 21 CISTPL_FUNCID 02 02 01 22 CISTPL_FUNCE 04 00 02 0F 7F Description Two functions Function 0 at offset 0x00A0 Function 1 at offset 0x140
OXCFU950 DATA SHEET
Manufacturer ID = 0x0279 Product ID = 0x952A
PC Card Standard 6.1 Manufacture Name = "CF CARD" Product Name = "GENERIC"
Contains ASCII text "CIS" so host knows that this is the start of a new valid chain
Serial Port
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Value (Hex) Tuple Name 1A CISTPL_CONFIG 05 01 07 00 02 6F 1B CISTPL_CFTABLE_ENTRY 0B C7 41 99 01 B5 1E 24 B0 FF FF 07 FF CISTPL_END Direct Attribute (Offset 0x0140) 13 CISTPL_LINKTARGET 03 43 49 53 21 CISTPL_FUNCID 02 0B 00 22 CISTPL_FUNCE 05 02 00 02 0C 00 1A CISTPL_CONFIG 05 01 07 00 03 6F 1B CISTPl_CFTABLE_ENTRY 0D C7 41 B9 01 B5 1E 26 B0 FF FF 08 00 07 FF CISTPL_END
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Description Last CFTABLE_ENTRY has index of 7 Base address of FCRs is 0x0200
Index 7 3.3 volts Any IRQ 16 bytes of I/O space.
Contains ASCII text "CIS" so host knows that this is the start of a new valid chain
OHCI USB Controller
Last CFTABLE_ENTRY has index of 7 Base address of FCRs is 0x0300
Index 7 3.3 volts Any IRQ 64 bytes of I/O space
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6.8.2
Standard Pre-Programmed CIS Image
(cfu950_multi_level_level_3v3_gold)
Description Common Memory: 4) SRAM 5) 200 ns 6) 1x2048 bytes Attribute Memory: 5) ROM 6) 200 ns 7) 1x512 bytes (CIS) 8) 1x512 bytes (Registers) Common Memory at 3.3 volts
Value (Hex) Tuple Name Direct Attribute (Offset 0x0000) 01 CISTPL_DEVICE 03 62 01 FF 17 CISTPL_DEVICE_A 05 12 00 D2 00 FF 1C CISTPL_DEVICE_OC 04 03 62 01 FF 1D CISTPL_DEVICE_OA 06 03 12 00 D2 00 FF 20 CISTPL_MANFID 04 79 02 2B 95 15 CISTPL_VERS_1 15 08 00 43 46 20 43 41 52 44 00 47 45 4E 45 52 49 43 00 00 00 FF
Attribute Memory at 3.3 volts
Manufacturer ID = 0x0279 Product ID = 0x952B
PC Card Standard 8.0 Manufacture Name = "CF CARD" Product Name = "GENERIC"
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06 CISTPL_LONGLINK_MFC 0B 02 00 50 00 00 00 00 A0 00 00 00 FF CISTPL_END Direct Attribute (Offset 0x00A0) 13 CISTPL_LINKTARGET 03 43 49 53 21 CISTPL_FUNCID 02 02 00 22 CISTPL_FUNCE 04 00 02 0F 7F 1A CISTPL_CONFIG 05 01 07 00 02 6F 1B CISTPL_CFTABLE_ENTRY 0D C7 41 99 01 B5 1E A4 40 0F B0 FF FF 07 FF CISTPL_END Direct Attribute (Offset 0x0140) 13 CISTPL_LINKTARGET 03 43 49 53 21 CISTPL_FUNCID 02 0B 00
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Two functions. Function 0 at offset 0x00A0 Function 1 at offset 0x140
Contains ASCII text "CIS" so host knows that this is the start of a new valid chain
Serial Port
Last CFTABLE_ENTRY has index of 7 Base address of FCRs is 0x0200
Index 7 3.3 volts Any IRQ 16 bytes of I/O space
Contains ASCII text "CIS" so host knows that this is the start of a new valid chain
OHCI USB Controller
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22 05 02 00 02 0C 00 1A 05 01 07 00 03 6F 1B 0F C7 41 B9 01 B5 1E A6 40 3F B0 FF FF 08 00 07 FF CISTPL_FUNCE
OXCFU950 DATA SHEET
CISTPL_CONFIG
Last CFTABLE_ENTRY has index of 7 Base address of FCRs is 0x0300
CISTPl_CFTABLE_ENTRY
Index 7 3.3 volts Any IRQ 64 bytes of I/O space
CISTPL_END
6.8.3
Example USB Single Function CIS Image
(cfu950_usb_level_3v3_gold)
The table below shows an example CIS image suitable for single-function USB operation at 3.3 V.
Value (Hex) Tuple Name Direct Attribute (Offset 0x0000) 01 CISTPL_DEVICE 03 62 01 FF 17 CISTPL_DEVICE_A 05 12 00 D2 00 FF 1C CISTPL_DEVICE_OC 04 03 62 01 FF Description Common Memory: 7) SRAM 8) 200 ns 9) 1x2048 bytes Attribute Memory: 9) ROM 10) 200 ns 11) 1x512 bytes (CIS) 12) 1x512 bytes (Registers) Common Memory at 3.3 volts
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1D 06 03 12 00 D2 00 FF 20 04 79 02 2B 95 21 02 FE 00 15 15 08 00 43 46 20 43 41 52 44 00 47 45 4E 45 52 49 43 00 00 00 FF 1A 05 01 07 00 03 6F CISTPL_DEVICE_OA Attribute Memory at 3.3 volts
OXCFU950 DATA SHEET
CISTPL_MANFID
Manufacturer ID = 0x0279 Product ID = 0x952B
CISTPL_FUNCID
CISTPL_VERS_1
PC Card Standard 8.0 Manufacture Name = "CF CARD" Product Name = "GENERIC"
CISTPL_CONFIG
Last CFTABLE_ENTRY has index of 7 Base address of FCRs is 0x0300
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1B 0F C7 41 B9 01 B5 1E A6 40 3F B0 FF FF 08 00 07 FF CISTPl_CFTABLE_ENTRY Index 7 3.3 volts Any IRQ 64 bytes of I/O space
OXCFU950 DATA SHEET
CISTPL_END
6.8.4
Example UART Single Function CIS Image
(cfu950_usb_pulse_5v_gold)
The table below shows an example CIS image suitable for single-function UART operation at 5 V.
Value (Hex) Tuple Name Direct Attribute (Offset 0x0000) 01 CISTPL_DEVICE 03 62 01 FF 17 CISTPL_DEVICE_A 05 12 00 D2 00 FF 1C CISTPL_DEVICE_OC 04 03 62 01 FF 1D CISTPL_DEVICE_OA 06 03 12 00 D2 00 FF 20 CISTPL_MANFID 04 79 02 2B 95 Description Common Memory: 10) SRAM 11) 200 ns 12) 1x2048 bytes Attribute Memory: 13) ROM 14) 200 ns 15) 1x512 bytes (CIS) 16) 1x512 bytes (Registers) Common Memory at 3.3 volts
Attribute Memory at 3.3 volts
Manufacturer ID = 0x0279 Product ID = 0x952B
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15 15 08 00 43 46 20 43 41 52 44 00 47 45 4E 45 52 49 43 00 00 00 FF 21 02 02 00 22 04 00 02 0F 7F 1A 05 01 07 00 02 6F 1B 0C C7 41 99 01 55 A4 40 0F D0 FF FF 07 FF CISTPL_VERS_1 PC Card Standard 8.0 Manufacture Name = "CF CARD" Product Name = "GENERIC"
OXCFU950 DATA SHEET
CISTPL_FUNCID
Serial Port
CISTPL_FUNCE
CISTPL_CONFIG
Last CFTABLE_ENTRY has index of 7 Base address of FCRs is 0x0200
CISTPL_CFTABLE_ENTRY
Index 7 5.0 volts Any IRQ 16 bytes of I/O space Pulsed interrupts
CISTPL_END
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OXCFU950 DATA SHEET
7
USB HOST CONTROLLER
To avoid this situation, an indirect access mechanism is used to allow the host PC to make atomic 32-bit accesses to the memory and USB register set. It allows the host PC to enter all details of the read or write operation, following which the device performs the operation in a single step. However, USB memory is also mapped into common memory space to allow the host PC to perform DMAs into the common memory area when there is no risk of the USB host controller reading invalid data. The indirect mechanism is also used to access the USB OHCI register set. For details of the operation of OHCI compatible USB hosts, refer to the OHCI standard. The USB host controller can be accessed via I/O space registers at offset 0x20 through 0x40, as shown below.
This datasheet assumes the reader has access to the public domain OHCI specification 1.0A, which is freely downloadable from the internet. It also assumes the reader has access to the USB Specification 2.0. Both documents can be downloaded from http://www.usb.org/developers/docs/ The OXCFU950 includes an embedded OHCI USB Host controller. The OHCI specification defines a standard way for a host system (e.g. a PCMCIA 16-bit PC Card host, such as a desktop or Laptop PC) to control a USB host. The OHCI specification defines a number of 32-bit registers and a data structure that exists in memory, to which both the host system and the USB host controller have access. The OXCFU950 CF interface does not support DMA-tohost memory, so an area of memory (the USB memory) is included on-chip and made available to the host system via the CompactFlash interface interface. The register set is mainly used during the setup of the USB host controller, and is not used a great deal during normal operation. The memory is accessed by both the OHCI controller and the CompactFlash interface host throughout USB operation. The OHCI specification assumes that both the memory and registers can be accessed via 32-bit atomic operations. This is not possible via the CompactFlash/CF+ or PCMCIA 16-bit PC Card interfaces, because only 8-bit and 16-bit operations are available. This could lead to problems, because the USB host controller assumes that the host PC uses 32-bit atomic operations to update the registers and the memory, when the host PC is making two 16-bit accesses or 4 8-bit accesses. Therefore, for a short time the 32-bit value consists of a number of bits of old data and a number of bits of new data--in effect, invalid data is potentially present in the USB registers.
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Offset from I/O base address (byte-based) 0x20 0x23 Name Register Address Register Control Description
OXCFU950 DATA SHEET
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x30 0x31 0x33
Register Write Data 0 Register Write Data 1 Register Write Data 2 Register Write Data 3 Register Read Data 0 Register Read Data 1 Register Read Data 2 Register Read Data 3 Memory Address 0 Memory Address 1 Memory Control
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C
Memory Write Data 0 Memory Write Data 1 Memory Write Data 2 Memory Write Data 3 Memory Read Data 0 Memory Read Data 1 Memory Read Data 2 Memory Read Data 3 Memory Page Select
0x3D
USB Coverage Reg 1
Address of USB Register to be indirectly read/written. (Quadlet address, i.e. 1, 2, 3 etc, not 0, 4, 8...) 7: if `1' then USB host controller is out of reset and ready for operation. 7: if `0' then USB host controller is in reset and not yet ready for operation. 6: reserved 5: reserved 4: reserved 3: reserved 2: reserved 1: if `1' then last write operation has been completed. 0: if `1' then it is safe to read contents of Register Read Data 0-3" Bits 7 down to 0 of 32-bit data to be written to the USB registers. Bits 15 down to 8 of 32-bit data to be written to the USB registers. Bits 23 down to 16 of 32-bit data to be written to the USB registers. Bits 31 down to 24 of 32-bit data to be written to the USB registers. Bits 7 down to 0 of 32-bit data to be read from the USB registers. Bits 15 down to 8 of 32-bit data to be read from the USB registers. Bits 23 down to 16 of 32-bit data to be read from the USB registers. Bits 31 down to 24 of 32-bit data to be read from the USB registers. Address of memory location to be indirectly read/written (bits 7 down to 0). Address of memory location to be indirectly read/written (bits 15 down to 8). 7: Reserved 6: Reserved 5: Reserved 4: Reserved 3: Reserved 2: Reserved 1: if `1' then last write operation has been completed. 0: if `1' then it is safe to read contents of Memory Read Data 0-3. Bits 7 down to 0 of 32-bit data to be written to the USB memory. Bits 15 down to 8 of 32-bit data to be written to the USB memory. Bits 23 down to 16 of 32-bit data to be written to the USB memory. Bits 31 down to 24 of 32-bit data to be written to the USB memory. Bits 7 down to 0 of 32-bit data to be read from the USB memory. Bits 15 down to 8 of 32-bit data to be read from the USB memory. Bits 23 down to 16 of 32-bit data to be read from the USB memory. Bits 31 down to 24 of 32-bit data to be read from the USB memory. 1:0 = "11" Page 3 (locations 6144-8191) selected. 1:0 = "10" Page 2 (locations 4096-6143) selected. 1:0 = "01" Page 1 (locations 2048-4095) selected. 1:0 = "00" Page 0 (locations 0-2047) selected. Bits 7 to 1 are readable and, if set, give the following information: 7: Common memory read has occurred since last reset. 6: Common memory write has occurred since last reset. 5: IAR RAM read has occurred since last reset. 4: HCI read has occurred since last reset. 3: HCI write (with at least one byte lane disabled) has occurred since last reset. 2: IAR RAM Write has occurred since last reset. 1: HCI write (no byte lanes disabled) has occurred since last reset. Bit 0 must be set to enable the USB coverage registers.
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0x3E USB Coverage Reg 2
OXCFU950 DATA SHEET
0x3F
USB Coverage Reg 3
Bits 7 to 0 are readable and, if set, show that the memory controller has been interrupted by a common memory read, while in the following states: 7: HCI_READ_RESULT 6: HCI_READ 5: CM_WRITE 4: CM_WRITE_PAUSE 3: HCI_WRITE 2: HCI_WRITE_PAUSE 1: CM_READ 0: IDLE Bits 1 to 0 are readable and, if set, show that the memory controller has been interrupted by a common memory read, while in the following states: 1: IAR_READ_RESULT 0: IAR_READ
Table 25: USB I/O Space Description
7.1
Writing to an OHCI Register in the Embedded USB Host Controller
* * *
The host must use the following procedure to write to a USB register: * Write the register offset into Register Address (0x20) * Write bits 7:0 of the 32 bit data value into Register Write Data 0 (0x24). * Write bits 15:8 of the 32 bit data value into Register Write Data 1 (0x25). * Write bits 23:16 of the 32 bit data value into Register Write Data 2 (0x26). * Write bits 31: 24 of the 32 bit data value into Register Write Data 3 (0x27). The 32-bit data value in Register Write Data 0-3 is written to the USB core in a single atomic transaction when a write to Register Write Data 3 occurs. On writing to Register Write Data 3, bit 1 of Register Control is cleared and set to 1 when the write is complete. This allows software to wait until the write has completed before continuing. This may be of use in checking that the USB host controller clock is running. Software is not required to check that this has happened.
Read bits 15:8 of the 32 bit data value from Register Read Data 1 (0x29). Read bits 23:16 of the 32 bit data value from Register Read Data 2 (0x2A). Read bits 31:24 of the 32 bit data value from Register Read Data 3 (0x2B).
The data read from the USB core is returned in the Register Read Data registers. The read is initiated every time a byte is written to Register Address.
7.3
Writing to the USB Memory
The host must use the following procedure to write to the USB memory: * Write the register offset into Memory Address (0x30 and 0x31) * Write bits 7:0 of the 32 bit data value into Memory Write Data 0 (0x34). * Write bits 15:8 of the 32 bit data value into Memory Write Data 1 (0x35). * Write bits 23:16 of the 32 bit data value into Memory Write Data 2 (0x36). * Write bits 31:24 of the 32 bit data value into Memory Write Data 3 (0x37). The 32-bit data value in Memory Write Data 0-3 is written to the USB memory in a single atomic transaction when a write to Memory Write Data 3 occurs. On writing to Memory Write Data 3, bit 1 of Memory Control is cleared and set to 1 when the write is complete, allowing software to wait until the write is complete before continuing. This may be of use in checking that the USB memory clock is running. Software is not required to check that this has happened.
7.2
Reading from an OHCI Register in the Embedded USB Host Controller
The host must use the following procedure to read from a USB register: * Write the register offset into Register Address (0x20) On writing to Register Address, bit 0 of Register Control is cleared and set to 1 when the read data is available for reading from Register Read Data 0-3. * Poll Register Control (0x23) & wait until bit 0 is set * Read bits 7:0 of the 32 bit data value from Register Read Data 0 (0x28).
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OXCFU950 DATA SHEET
7.4
Reading from USB Memory
7.6
USB Host Controller Overview
The host must use the following procedure to read from USB memory: * Write the memory address into Memory Address 0 and Memory Address 1. On writing to Memory Address 1, bit 0 of Memory Control is cleared and set to 1 when the read data is available for reading from Memory Read Data 0-3. * * * * * Poll Memory Control (0x33) & wait until bit 0 is set. Read bits 7:0 of the 32 bit data value from Memory Read Data 0 (0x38). Read bits 15:8 of the 32 bit data value from Memory Read Data 1 (0x39). Read bits 23:16 of the 32 bit data value from Memory Read Data 2 (0x3A). Read bits 31:24 of the 32 bit data value from Memory Read Data 3 (0x3B).
The OXCFU950 USB module uses an OHCI-compliant USB host controller. This is augmented by a 2-Kbyte x 32bit RAM to which both the OHCI controller and the host machine have access. The host access can be direct via common memory space or indirect via I/O space. A USB RAM controller arbitrates between all three sources of RAM read and writes. The priority of the accesses is shown below (most important first): 1) CF host read--has to be highest priority because there are strict requirements of the CF bus to be met. A CF host read access interrupts and pauses any other accesses. All other accesses can be held off, and so do not interrupt a lower priority access. 2) OHCI read/write--the USB host controller should generally be given priority. 3) CF write access--because this can be queued until the OHCI read/write has been completed. 4) Indirect I/O access--lowest priority because this can easily be held off, and doing so should not adversely affect performance. The RAM controller is responsible for this arbitration.
The data read from USB memory is returned in Memory Read Data 0-3. The read is initiated every time Memory Address 1 is written.
7.5
Accessing USB Memory via Common Memory Access
Due to the limited number of address bits available in the compact flash form factor (11 address bits) a paging mechanism must be used if direct access to the USB Memory (via common memory space) is required. It should be used as follows. To access a portion of the USB memory via the common memory space the host system should follow this procedure: * Select the portion of USB memory via the Memory Page Select (0x40) register. * Access the page of memory via common memory space (location 0x0000-0x07FF).
The HCI bus controller is responsible for communicating with the UHOSTC. Local bus indirect access can be generated either to the UHOSTC register set or to the RAM. The HCI bus controller must direct these accesses appropriately. Note: The USB controller supports all OHCI endpoint types. However, support is not provided for USB hub devices.
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OXCFU950 DATA SHEET
8
UART INTERFACE
The internal UART in the OXCFU950 is based on that used in the well-proven OX16C95x UARTs, but with a number of significant enhancements. It is referred to throughout this document as the OXCFU950 UART core, or simply UART.
8.1
Mode Selection
The OXCFU950 UART is software-compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the 950 depends on a number of modes which are referenced throughout this data sheet. The FIFO depth and compatibility modes are tabulated below:
UART Mode 450 550 650 750 950* FIFO size 1 16 128 128 128 FiCR[0] 0 1 1 1 1 Enhanced mode (EFR[4]=1) X 0 1 0 1 FiCR[5] (guarded with LCR[7] = 1) X 0 X 1 X
* Note that 950 mode configuration is identical to 650 configuration
Table 12: UART Mode Configuration
8.1.1
450 Mode
8.1.4
650 Mode
After a hardware reset, bit 0 of the FiCR is cleared, making the 950 compatible with the 16C450. The transmitter and receiver FIFOs (referred to as the Transmit Holding Register and Receiver Holding Register respectively) have a depth of one. This is referred to as byte mode. When FiCR[0] is cleared, all other mode selection parameters are ignored.
The 950 is compatible with the 16C654 when EFR[4] is set, i.e., the device is in enhanced mode. Because 650 software drivers usually put the device into enhanced mode, running 650 drivers on the 950 results in 650 compatibility with 128-deep FIFOs, as long as FiCR[0] is set. Note that the 650 emulation mode of the 950 provides 128-byte deep FIFOs whereas the standard 16C654 has only 32 byte FIFOs. 650 mode has the same enhancements as the 16C750 over the 16C550, but these are enabled using different registers. There are also additional enhancements over those of the 16C750 in this mode, these are: 1. 2. 3. 4. 5. Automatic in-band flow control Special character detection Infra-red IrDA format transmit and receive mode Transmit trigger levels Optional clock prescaler
8.1.2
550 Mode
After a hardware reset, writing a 1 to FiCR[0] increases the FIFO size to 16, providing compatibility with 16C550 devices.
8.1.3
750 Mode
Writing a 1 to FiCR[0] increases the FIFO size to 16. In a similar fashion to 16C750, the FIFO size can be further increased to 128 by writing a 1 to FiCR[5]. Note that access to FiCR[5] is protected by LCR[7]; i.e., to set FiCR[5], software should first set LCR[7] to remove the guard temporarily. When FiCR[5] is set, software should clear LCR[7] for normal operation. The 16C750 additional features over the 16C550 are available as long as the UART is not put into Enhanced mode (i.e. EFR[4] should be 0). These features are: 1. Deeper FIFOs 2. Automatic RTS/CTS out-of-band flow control
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OXCFU950 DATA SHEET
8.1.5
950 Mode
The additional features offered in 950 mode generally only apply when the UART is in enhanced mode (EFR[4]=1). Provided FiCR[0] is set, in enhanced mode the FIFO size is 128. Note that 950 mode configuration is identical to that of 650 mode, however additional 950-specific features are enabled using the Additional Control Register (ACR) (see section 8.11.3). In addition to larger FIFOs and higher baud rates, the enhancements of the 950 over the 16C654 are: * * * * * * * * * * * * * Selectable arbitrary trigger levels for the receiver and transmitter FIFO interrupts Improved automatic flow control using selectable arbitrary thresholds DSR#/DTR# automatic flow control Transmitter & receiver can be optionally disabled Software reset of device Readable FIFO fill levels Optional generation of an RS-485 buffer enable signal Four-byte device identification (0x16C95011) Readable status for automatic in-band and out-ofband flow control Flexible M N/8 clock prescaler (see section 8.10.2) Fixed 48-MHz clock input from internal PLL (12-MHz crystal input multiplied by 4) Programmable sample clock to allow data rates up to 12 Mbps (see section 8.10.3) 9-bit data mode
The UART has a flexible prescaler capable of dividing the system clock by any value between 1 and 31.875 in steps of 0.125. It divides the system clock by an arbitrary value in M N/8 format, where M and N are 5- and 3-bit binary numbers programmed in CPR[7:3] and CPR[2:0] respectively. This arrangement offers a great deal of flexibility when choosing how to synthesize arbitrary baud rates. The default division value is 4 to provide backward compatibility with 16C654 devices. It is also possible to define the over-sampling rate used by the transmitter and receiver clocks. The 16C450/16C550 and compatible devices employ 16 times over-sampling, i.e., there are 16 clock cycles per bit. However, the 950 can employ any over-sampling rate from 4 to 16 by programming the TCR register. The default value after a reset for this register is 0x00, which corresponds to a 16cycle sampling clock. Writing 0x01, 0x02 or 0x03 also results in a 16-cycle sampling clock. To program the value to any value from 4 to 15 it is necessary to write this value into TCR. For example, to set the device to a 13 cycle sampling clock it would be necessary to write 0x0D to TCR. For further information see section 8.10.3. The 950 also offers 9-bit data frames for multi-drop industrial applications.
The 950 trigger levels are enabled when ACR[5] is set (bits 4 to 7 of FiCR are ignored). Then arbitrary trigger levels can be defined in RTL, TTL, FCL and FCH registers (see section 8.11). The Additional Status Register (ASR) offers flow control status for the local and remote transmitters. FIFO levels are readable using RFL and TFL registers.
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OXCFU950 DATA SHEET
8.2
Register Description Tables
The UART registers are accessible from the host machine I/O space. In order to support legacy software, selection of the registers is also dependent on the state of the LCR and ACR: 1. LCR[7]=1 enables the divider latch registers DLL and DLM. 2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. 3. ACR[7]=1 enables access to the 950 specific registers. 4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 43.
Register Name THR 1 RHR 1 IER 1,2 650/950 Mode 550/750 Mode FiCR 3 650 mode 750 mode 950 mode ISR 3 LCR 4 MCR 3,4 550/750 Mode 650/950 Mode LSR 3,5 Normal 9-bit data mode MSR 3 0x05 R 0x02 0x03 R R/W FIFOs enabled Divisor latch access Tx break 0x02 W Address0 0x00 0x00 R/ W W R CTS interrupt mask RTS interrupt mask Unused RHR Trigger Level RHR Trigger Level Unused Interrupt priority (Enhanced mode) Force parity CTS & RTS Flow Control XON-Any THR Empty Odd / even parity Internal Loop Back Enable Rx Break Parity enable THR Trigger Level FIFO Unused Size Special Char. Detect Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data to be transmitted Data received Modem interrupt mask DMA Mode / Tx Trigger Enable Rx Stat interrupt mask THRE interrupt mask RxRDY interrupt mask
0x01
R/W
Unused
Flush THR
Flush RHR
Enable FIFO
Interrupt priority (All modes) Number of stop bits
Interrupt pending Data length
Unused 0x04 R/W Baud prescale Data Error IrDA mode Tx Empty
OUT2 (Int En)
OUT1
RTS
DTR
Framing Error
Parity Error
Overrun Error
RxRDY
0x06
R
DCD
RI
SPR 3 Normal 0x07 R/W 9-bit data Unused mode Additional Standard Registers - These registers require divisor latch access bit (LCR[7]) to be set to 1. DLL DLM 0x00 0x01 R/W R/W Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte)
9th Rx data bit Delta Trailing DSR CTS DCD RI edge Temporary data storage register and Indexed control register offset value bits
Delta DSR
Delta CTS
9th Tx data bit
Table 13: Standard 550-Compatible Registers
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OXCFU950 DATA SHEET
Register Address R/W Bit 7 Bit 6 Name To access these registers LCR must be set to 0xBF EFR 010 R/W CTS RTS flow Flow control control XON1 100 R/W 9-bit mode XON2 9-bit mode XOFF1 9-bit mode XOFF2 9-bit mode 101 110 111 R/W R/W R/W
Bit 5 Special char detect
Bit 4 Enhanced mode
Bit 3
Bit 2
Bit 1
Bit 0
In-band flow control mode
XON Character 1 Special character 1 XON Character 2 Special Character 2 XOFF Character 1 Special character 3 XOFF Character 2 Special character 4
Table 14: 650 Compatible Registers
Register Name ASR 1,6,7 RFL 6, 10 TFL 3,6, 10 ICR 3,8,9
Address 001 011 100 101
R/W R/W 7 R R R/W
Bit 7 Tx Idle
Bit 6 FIFO size
Bit 5 `0'
Bit 4
Bit 3
Bit 2
Bit 1 Remote Tx Disabled
Bit 0 Tx Disabled
Special DTR RTS Char Detect Number of characters in the receiver FIFO Number of characters in the transmitter FIFO
Data read/written depends on the value written to the SPR prior to the access of this register (see Table 17)
Table 15: 950 Specific Registers
Address0 0x0811 to 0x0B 0x0C TFL10 RFL10 GDS10 0x0D 0x0E 0x0F R R R
Register Name 32-bit11 FIFO Access registers
R/ W W R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
On any write to these registers a byte will be written to the TX FIFO. Writing any of these locations is functionally the same as writing to THR (Address offset 0x00). On any read of these registers a byte will be returned from the RX FIFO. Reading any of these locations is functionally the same as reading RHR (Address offset 0x00). This location is not assigned to the UART Returns the Tx FIFO fill level. Returns the Rx FIFO fill level. Good Data Status
Table 16: OXCFU950 Specific Registers
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Register access notes:
Note 0: Offset from function base address in I/O space Note 1: Requires LCR[7] = 0 Note 2: Requires ACR[7] = 0 Note 3: Requires that last value written to LCR was not 0xBF Note 4: To read this register ACR[7] must be = 0 Note 5: To read this register ACR[6] must be = 0 Note 6: Requires ACR[7] = 1 Note 7: Only bits 0 and 1 of this register can be written Note 8: To read this register ACR[6] must be = 1 Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set Note 10: TFL, RFL and GDS are available at two locations, accessing via the OXCFU950 specific register location being the most simple Note 11: The 32-bit FIFO Access registers can also be accessed at 0x00 through 0x03, when DBURST is set to 0x01. This is for systems where the UART must be mapped to an 8-byte address space. Register SPR R/W Name Offset 12 Indexed Control Register Set ACR 0x00 R/W Bit 7 Additiona l Status Enable Bit 6 ICR Read Enable Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPR TCR TTL RTL FCL FCH ID1 ID2 ID3 REV CSR NMR MDM RFC GDS13 DMS
0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0X0F 0X10 0x11
R/W R/W R/W R/W R/W R/W R/W R R R R W R/W R/W R R R/W FiCR[7] Unused Unused Unused Unused Unused
950 DTR definition and Trigger control Level Enable 5-bit integer part of clock prescaler Unused
AutoDSR Tx Rx Flow Disable Disable Control Enable 3-bit fractional part of clock prescaler 4 Bit N-times clock selection bits [3:0]
Unused Transmitter Interrupt Trigger Level (0-127) Receiver Interrupt Trigger Level (1-127) Automatic Flow Control Lower Trigger Level (0-127) Automatic Flow Control Higher Trigger level (1-127) Hardwired ID byte 1 (0x16) Hardwired ID byte 1 (0xC9) Hardwired ID byte 1 (0x50) Hardwired revision byte (0x0B) Writing 0x00 to this register will reset the UART 9th Bit SChar 4 9th Bit Schar 3 Disable wake-up
sensitivity
Unused FiCR[6] FiCR[5]
FiCR[4] Unused
9th Bit SChar 2 DCD Wakeup disable FiCR[3]
9th Bit SChar 1 Trailing RI edge disable FiCR[2]
9th-bit Int. En. DSR Wakeup disable FiCR[1]
Force internal TxRdy inactive
Force internal RxRdy inactive
Unused Hardwired Port Index ( 0x00 ) Unused
Internal TxRdy status (R)
9 Bit Enable CTS Wakeup disable FiCR[0] Good Data Status Internal RxRdy status (R)
PIDX
0x12 0x13
R R/W
Table 17: Indexed Control Register Set
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Note 12: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the indexed control registers via ICR. Offset values not listed in the table are reserved for future use and must not be used. To read or write to any of the Indexed Control Registers use the following procedure. Writing to ICR registers: Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value). Write the desired offset to SPR (address 1112). Write the desired value to ICR (address 1012). Reading from ICR registers: Ensure that the last value written to LCR was not 0xBF (see above). Write 0x00 offset to SPR to select ACR. Set bit 6 of ACR (ICR read enable) by writing x1xxxxxx2 to address 1012. Ensure that other bits in ACR are not changed. (Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!) Write the desired offset to SPR (address 1112). Read the desired value from ICR (address 1012). Write 0x00 offset to SPR to select ACR. Clear bit 6 of ACR bye writing x0xxxxxx2 to ICR, thus enabling access to standard registers again. Note 13: GDS available directly in OXCFU950 specific register space at 0x0F Register SPR R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Name Offset 11 Indexed Control Register Set - alternative baud rate control registers A_LATCH 0x30 R/W To access addresses 0x31 to 0x35 in this alternative register set the value 0xEB must be written to this location. A_ENABLE 0x31 R/W Enables Enables Enables A_TCR A_CPR A_DLM A_DLL 0x32 R/W Alternative DLL register. A_DLM A_CPR A_TCR 0x33 0x34 0x35 0x36 0x37 R/W R/W R/W Alternative DLM register. Alternative CPR register. Alternative TCR register. Unused Unused Bit 0
Enables A_DLL
Indexed Control Register Set - Alternative 32-bit FIFO access registers enable DBURST 0x38 Unused
DBURST Enable
Table 18: OXCFU950 Specific Alternative UART Baud Rate Control Registers Table 18 shows the set of OXCFU950 specific alternative UART baud rate control registers, which can be used instead of the standard versions of these registers. This facility prevents legacy drivers with knowledge of the 950 UART register set from making incorrect assumptions about the OXCFU950 crystal frequency and synthesizing incorrect baud rate values by writing to the standard DLL, DLM, CPR and TCR registers. It also shows the Alternative 32-bit FIFO Access Registers Enable.
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8.3
8.3.1
Reset Configuration
Host Reset
The reset state of output signals are tabulated below:
Signal SOUT RTS# DTR# Reset state Inactive High Inactive High Inactive High
After a hardware reset or soft reset (bit 7 of COR register), all writable registers are reset to 0x00, with the following exceptions: 1. DLL--reset to 0x01. 2. CPR--reset to 0x20. The state of read-only registers following a hardware reset is as follows: RHR[7:0]: RFL[6:0]: TFL[6:0]: LSR[7:0]: MSR[3:0]: MSR[7:4]: ISR[7:0]: ASR[7:0]: RFC[7:0]: GDS[7:0]: DMS[7:0]: Indeterminate 00000002 00000002 0x60 signifying that both the transmitter and the transmitter FIFO are empty 00002 Dependent on modem input lines DCD, RI, DSR and CTS respectively 0x01, i.e. no interrupts are pending 1xx000002 000000002 000000012 000000102
Table 19: Output Signal Reset State
8.3.2
Software Reset
An additional feature available in the 950 core is software resetting of the serial channel. The software reset is available using the CSR register. Software reset has the same effect as a hardware reset. To reset the UART, write 0x00 to the CSR.
8.4
Transmitter & Receiver FIFOs
Data written to the THR when it is full is lost. Data read from the RHR when it is empty is invalid. The empty or full status of the FIFOs is indicated in LSR (see section 8.5.3). Interrupts can be generated or DMA signals can be used to transfer data to/from the FIFOs. The number of items in each FIFO may also be read back from the transmitter FIFO level (TFL) and receiver FIFO level (RFL) registers (see section 8.11.2).
The transmitter and receiver holding registers (FIFOs), are referred to as THR and RHR respectively. In normal operation, when the transmitter finishes transmitting a byte it removes the next data from the top of the THR and transmits it. If the THR is empty, it waits until data is written into it. If THR is empty and the last character transmission is complete (i.e. the transmitter shift register is empty) the transmitter is said to be idle. Similarly, when the receiver finishes receiving a byte, it transfers it to the bottom of the RHR. If the RHR is full, an overrun condition occurs (see section 8.5.3). Data is written into the bottom of the THR queue and read from the top of the RHR queue completely asynchronously to the operation of the transmitter and receiver. FIFO size depends on the setting of the FiCR register. In byte mode, FIFOs only accept one byte at a time before indicating that they are full; this is compatible with the 16C450. In a FIFO mode, the size of the FIFOs is either 16 (compatible with the 16C550) or 128.
8.4.1
4-Byte Access to THR & RHR
As with the OX16C95x UARTs, the OXCFU950 THR and RHR registers can be accessed via the standard 550 compatible register space. See Table 13. In the OXCFU950, the THR and RHR registers can also be accessed at four contiguous locations in the OXCFU950 specific register locations. See Table 16. Note: the same RHR data is read irrespective of which of the four byte locations are read. Similarly, writing to any of the additional THR locations has the same effect as writing to any other--all four locations provide duplicate addresses to the same THR or RHR register.
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This enables the host CPU to initiate a 32-bit access to the word address of the replicated THR or RHR locations. This is broken down into four separate byte-size accesses by the system PC Card or CF controller. Because each byte is individually accessed, the FIFO is shifted in the manner previously described. The DBURST register is provided to support this feature in systems where only an 8-byte UART address space is available. Writing 1 to bit 0 of the DBURST register enables address locations 0x00 through 0x03 to be used in the same way as locations 0x08 through 0x0B. Although the number of accesses made to the OXCFU950 register set is not changed, host CPU utilization is reduced and maximum data throughput across the PC Card or CF interface is increased.
OXCFU950 DATA SHEET
450, 550 and extended 550 modes: The transmitter interrupt trigger levels are set to 1 and FiCR[5:4] are ignored. 650 mode: In 650 mode the transmitter interrupt trigger levels are set to the following values:
FiCR[5:4] 00 01 10 11 Transmit Interrupt Trigger level 16 32 64 112
Table 20: Transmit Interrupt Trigger Levels These levels only apply to enhanced mode and DMA mode 1 (FiCR[3] = 1), otherwise the trigger level is set to 1. A transmitter empty interrupt will be generated (if enabled) if the TFL falls below the trigger level. 750 Mode: In 750 compatible non-enhanced (EFR[4]=0) mode, transmitter trigger level is set to 1, FiCR[4] is unused and FiCR[5] defines the FIFO depth as follows: FiCR[5]=0 transmitter and receiver FIFO size is 16 bytes. FiCR[5]=1 transmitter and receiver FIFO size is 128 bytes. In non-enhanced mode FiCR[5] is only writable when LCR[7] is set. Note: in enhanced mode, the FIFO size is also increased to 128 bytes when FiCR[0] is set. 950 mode: Setting ACR[5] to 1 enables arbitrary transmitter trigger level setting using the TTL register (see section 8.11.4), so FiCR[5:4] are ignored. FiCR[7:6]: RHR trigger level In 550, extended 550, 650 and 750 modes, the receiver FIFO trigger levels are defined using FiCR[7:6]. The interrupt trigger level and upper flow control trigger level where appropriate are defined by L2 in the table below. L1 defines the lower flow control trigger level where applicable. Separate upper and lower flow control trigger levels introduce a hysteresis element in in-band and out-ofband flow control (see section 8.9).
8.4.2
FIFO Control Register--FiCR
FiCR[0]: Enable FIFO mode logic 0 Byte mode. logic 1 FIFO mode. This bit should be enabled before setting the FIFO trigger levels. FiCR[1]: Flush RHR logic 0 No change. logic 1 Flushes the contents of the RHR This is only operative in a FIFO mode. The RHR is flushed automatically whenever changing between Byte mode and a FIFO mode. This bit returns to zero after clearing the FIFOs. FiCR[2]: Flush THR logic 0 No change. logic 1 Flushes the contents of the THR in the same manner as FiCR[1] does for the RHR.
DMA Transfer Signaling:
FiCR[3]: DMA signaling mode / Tx trigger level enable logic 0 DMA mode 0. logic 1 DMA mode 1. DMA signals are not bonded out in the OXCFU950, so this control only affects the transmitter trigger level in DMA mode 0. FiCR[5:4]: THR trigger level Generally in 450, 550, extended 550 and 950 modes these bits are unused (see section 8.1 for mode definition). In 650 mode they define the transmitter interrupt trigger levels and in 750 mode FiCR[5] increases the FIFO size.
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FiCR [7:6] 650 FIFO Size 128 L1 L2 1 16 16 32 32 112 112 120
Mode 750 FIFO Size 128 L1 L2 1 1 1 32 1 64 1 112 550 FIFO Size 16 L1 L2 n/a 1 n/a 4 n/a 8 n/a 14
In byte mode (450 mode) the trigger levels are all set to 1. In all cases, a receiver data interrupt is generated (if enabled) if the Receiver FIFO Level (RFL) reaches the upper trigger level L2. 950 Mode: When 950 trigger levels are enabled (ACR[5]=1), more flexible trigger levels can be set by writing to the TTL, RTL, FCL and FCH (see section 8.11) hence ignoring FiCR[7:6].
00 01 10 11
Table 21: Receiver Trigger Levels
8.5
8.5.1
Line Control & Status
False Start Bit Detection
LCR[2]: Number of stop bits LCR[2] defines the number of stop bits per serial character.
LCR[2] 0 1 1 Data length 5,6,7,8 5 6,7,8 No. stop bits 1 1.5 2
On the falling edge of a start bit, the receiver waits for 1/2 bit and then resynchronizes the receiver's sampling clock to the centre of the start bit. The start bit is valid if the SIN line is still low at this mid-bit sample and the receiver proceeds to read in a data character. Verifying the start bit prevents the receiver from assembling a false data character due to a low going noise spike on the SIN input. When the first stop bit is sampled, the received data is transferred to the RHR and the receiver waits for a low transition on SIN signifying the next start bit. The receiver continues to receive data even if the RHR is full or has been disabled (see section 8.11.3) in order to maintain framing synchronization. The only difference is that the received data is not transferred to the RHR.
Table 23: LCR Stop Bit Number Configuration LCR[5:3]: Parity type The selected parity type will be generated during transmission and checked by the receiver, which may produce a parity error as a result. In 9-bit mode parity is disabled and LCR[5:3] is ignored.
LCR[5:3] xx0 001 011 101 111 Parity type No parity bit Odd parity bit Even parity bit Parity bit forced to 1 Parity bit forced to 0
8.5.2
Line Control Register--LCR
The LCR specifies the data format that is common to both transmitter and receiver. Writing 0xBF to LCR enables access to the EFR, XON1, XOFF1, XON2 and XOFF2, DLL and DLM registers. This value (0xBF) corresponds to an unused data format. Writing the value 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. LCR[1:0]: Data length LCR[1:0] Determines the data length of serial characters. Note however, that these values are ignored in 9-bit data framing mode, i.e. when NMR[0] is set.
LCR[1:0] 00 01 10 11 Data length 5 bits 6 bits 7 bits 8 bits
Table 24: LCR Parity Configuration LCR[6]: Transmission break logic 0 Break transmission disabled. logic 1 Forces the transmitter data output SOUT low to alert the communication terminal, or send zeros in IrDA mode. The software driver must ensure that the break duration is longer than the character period for it to be recognized remotely as a break rather than data. LCR[7]: Divisor latch enable logic 0 Access to DLL & DLM registers disabled. logic 1 Access to DLL & DLM registers enabled.
Table 22: LCR Data Length Configuration
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8.5.3
Line Status Register--LSR
This register provides the status of data transfer to CPU. LSR[0]: RHR data available logic 0 RHR is empty: no data available logic 1 RHR is not empty: data is available to be read. LSR[1]: RHR overrun error logic 0 No overrun error. logic 1 Data was received when the RHR was full. An overrun error has occurred. The error is flagged when the data would normally have been transferred to the RHR. LSR[2]: Received data parity error logic 0 No parity error in normal mode or 9th bit of received data is 0 in 9-bit mode. logic 1 Data has been received that did not have correct parity in normal mode or 9th bit of received data is `1' in 9-bit mode. The flag is set when the data item in error is at the top of the RHR, and cleared following a read of the LSR. In 9-bit mode, LSR[2] is no longer a flag and corresponds to the 9th bit of the received data in RHR. LSR[3]: Received data framing error logic 0 No framing error. logic 1 Data was received with an invalid stop bit. This status bit is set and cleared in the same manner as LSR[2]. When a framing error occurs, the UART tries to resynchronize by assuming that the error was due to sampling the start bit of the next data item. LSR[4]: Received break error logic 0 No receiver break error. logic 1 The receiver received a break.
A break condition occurs when the SIN line goes low (normally signifying a start bit) and stays low throughout the start, data, parity and first stop bit. (Note: the SIN line is sampled at the bit rate). A zero character with associated break flag set is transferred to the RHR, and the receiver then waits until the SIN line returns high. The LSR[4] break flag is set when this data item gets to the top of the RHR and is cleared following a read of the LSR. LSR[5]: THR empty logic 0 Transmitter FIFO (THR) is not empty. logic 1 Transmitter FIFO (THR) is empty. LSR[6]: Transmitter and THR empty logic 0 The transmitter is not idle logic 1 THR is empty and the transmitter has completed the character in shift register and is in idle mode. (I.e. set whenever the transmitter shift register and the THR are both empty.) LSR[7]: Receiver data error logic 0 Either there are no receiver data errors in the FIFO or it was cleared by an earlier read of LSR. logic 1 At least one parity error, framing error or break indication in the FIFO. In 450 mode LSR[7] is permanently cleared, otherwise this bit is set when an erroneous character is transferred from the receiver to the RHR. It is cleared when the LSR is read. Note that in 16C550 this bit is only cleared when all of the erroneous data are removed from the FIFO. In 9-bit data framing mode parity is permanently disabled, so this bit is not affected by LSR[2].
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8.6
UART Interrupts
The serial interrupt on the OXCFU950 is routed to the OXCFU950 interrupt control, regardless of MCR[3].
In 16C654-compatible mode, when the device is in enhanced mode (EFR[4]=1), this bit enables the detection of special characters. It enables both the detection of XOFF characters (when in-band flow control is enabled via EFR[3:0]) and the detection of the XOFF2 special character (when enabled via EFR[5]). 750 mode (non-9-bit data framing): logic 0 Disable alternative sleep mode. logic 1 Enable alternative sleep mode whereby the internal clock of the channel is switched off. IER[6]: RTS interrupt mask logic 0 Disable the RTS interrupt. logic 1 Enable the RTS interrupt. This enable is only operative in enhanced mode (EFR[4]=1). In non-hnhanced mode, RTS interrupt is permanently enabled. IER[7]: CTS interrupt mask logic 0 Disable the CTS interrupt. logic 1 Enable the CTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, CTS interrupt is permanently enabled.
Note 0: In the OX16C95x UARTs this bit is used for sleep mode. In the OXCFU950, sleep management is managed outside of the UART. See 8.6.4. The OXCFU950 UART core has all standard 950 power management features removed, so that a single clock domain solution is possible, so sleep mode with this device is not possible. Most OS support for power management in UART devices is based on waking the device up on a modem event such as a falling edge on ring indicator (RI). The UART core contains a single flip-flop that is not on the standard clock domain, allowing events like these to be signaled to the surrounding logic, even when the clock is not running. Note 1: In the OX16C95x UARTs 16C750-compatible mode this bit is used as an alternative sleep mode, whcih is not the case with the OXCFU950
8.6.1
Interrupt Enable Register--IER
Serial channel interrupts are enabled using the Interrupt Enable Register (IER). IER[0]: Receiver data available interrupt mask logic 0 Disable the receiver ready interrupt. logic 1 Enable the receiver ready interrupt. IER[1]: Transmitter empty interrupt mask logic 0 Disable the transmitter empty interrupt. logic 1 Enable the transmitter empty interrupt. IER[2]: Receiver status interrupt Normal mode: logic 0 Disable the receiver status interrupt. logic 1 Enable the receiver status interrupt. 9-bit data mode: logic 0 Disable receiver status & address bit interrupt. logic 1 Enable receiver status & address bit interrupt. In 9-bit mode (i.e. when NMR[0] is set) reception of a character with the address-bit (9th bit) set can generate a level 1 interrupt if IER[2] is set. IER[3]: Modem status interrupt mask logic 0 Disable the modem status interrupt. logic 1 Enable the modem status interrupt. IER[4]: Reserved0 IER[5]: Special character interrupt mask1 9-bit data framing mode: logic 0 Disable the special character receive interrupt. logic 1 Enable the special character receive interrupt. In 9-bit data mode, The receiver can detect up to four special characters programmed in Special Character 1 to 4. When IER[5] is set, a level 5 interrupt is asserted when a match is detected. 650/950 modes (non-9-bit data framing): logic 0 Disable the special character receive interrupt. logic 1 Enable the special character receive interrupt.
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8.6.2
Interrupt Status Register--ISR
Level 2b:
Receiver time-out interrupt (ISR[5:0]='001100'): A receiver time-out event, which may cause an interrupt, will occur when all of the following conditions are true: * The UART is in a FIFO mode * There is data in the RHR. * There has been no read of the RHR for a period of time greater than the time-out period. * There has been no new data received and written into the RHR for a period of time greater than the time-out period. The time-out period is four times the character period (including start and stop bits) measured from the centre of the first stop bit of the last data item received. Reading the first data item in RHR clears this interrupt.
100000
The source of the highest priority interrupt pending is indicated by the contents of the interrupt status register ISR. There are nine sources of interrupt at six levels of priority (1 is the highest) as tabulated below:
Level 1 2a 2b 3 4 52 Interrupt source No interrupt pending 1 Receiver status error or Address-bit detected in 9-bit mode Receiver data available Receiver time-out Transmitter THR empty Modem status change In-band flow control XOFF or Special character (XOFF2) or Special character 1, 2, 3 or 4 or bit 9 set in 9-bit mode CTS or RTS change of state ISR[5:0]
see note 3
000001 000110 000100 001100 000010 000000 010000
62
Level 3:
Transmitter empty interrupt (ISR[5:0]='000010'): This interrupt is set when the transmit FIFO level falls below the trigger level. It is cleared on an ISR read of a level 3 interrupt or by writing more data to the THR so that the trigger level is exceeded. Note that when 950 mode trigger levels are enabled (ACR[5]=1) and the transmitter trigger level of zero is selected (TTL=0x00), a transmitter empty interrupt is only asserted when both the transmitter FIFO and transmitter shift register are empty and the SOUT line has returned to idle marking state.
Table 25: Interrupt Status Identification Codes
Note1: Note2: Note3: ISR[0] indicates whether any interrupts are pending. Interrupts of priority levels 5 and 6 cannot occur unless the UART is in Enhanced mode. ISR[5] is only used in 650 & 950 modes. In 750 mode, it is 0 when FIFO size is 16 and 1 when FIFO size is 128. In all other modes it is permanently set to 0.
8.6.3 Level 1:
Interrupt Description
Level 4:
Modem change interrupt (ISR[5:0]='000000'): This interrupt is set by a modem change flag (MSR[0], MSR[1], MSR[2] or MSR[3]) becoming active due to changes in the input modem lines. This interrupt is cleared following a read of the MSR.
Receiver status error interrupt (ISR[5:0]='000110'): Normal (non-9-bit) mode: This interrupt is active whenever any of LSR[1], LSR[2], LSR[3] or LSR[4] are set. These flags are cleared following a read of the LSR. This interrupt is masked with IER[2]. 9-bit mode: This interrupt is active whenever any of LSR[1], LSR[2], LSR[3] or LSR[4] are set. The receiver error interrupt due to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The `address-bit' received interrupt is masked with NMR[1]. The software driver can differentiate between receiver status error and received address-bit (9th data bit) interrupt by examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only set when LSR[3] or LSR[4] is set and it is not affected by LSR[2] (i.e. 9th data bit).
Level 5:
Receiver in-band flow control (Xoff) detect interrupt, Receiver special character (Xoff2) detect interrupt, Receiver special character 1, 2, 3 or 4 interrupt or 9th Bit set interrupt in 9-bit mode (ISR[5:0]=010000): A level 5 interrupt can only occur in enhanced-mode when any of the following conditions are met: * A valid Xoff character is received while in-band flow control is enabled. * A received character matches Xoff2 while special character detection is enabled. * A received character matches special character 1, 2, 3 or 4 in 9-bit mode (see section 8.11.8). It is cleared on an ISR read of a level 5 interrupt.
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Level 2a:
Receiver data available interrupt (ISR[5:0]='000100'): This interrupt is active whenever the receiver FIFO level is above the interrupt trigger level.
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Level 6:
CTS or RTS changed interrupt (ISR[5:0]=100000): This interrupt is set whenever either of the CTS# or RTS# pins changes state from low to high. It is cleared on an ISR read of a level 6 interrupt.
8.6.4
UART Power Saving
UART power saving is facilitated by the OXCFU950 selectively disabling the clock supplied to the OXCFU950 UART core. The wake-up signal can be sensitive to any of the following events * Falling edge of RI * Delta CTS * Delta DSR * Delta DCD The sensitivity to each of these events is controlled by the modem disable mask register (MDM) The MDM register is located at offset 0x0E of the ICR This register is cleared after a hardware reset to maintain compatibility with 16C550. It allows the user to mask interrupts and control wake-up operation due to individual modem lines.
To initiate UART power saving correctly: * Ensure there are no outstanding interrupts * Set MDM to enable the desired wake-up events (e.g. set to 0x0B for RI sensitivity only). This may be set up permanently elsewhere if different sensitivity for the modem status interrupt is not required under normal running operation * Read the MSR * Read the MSR again, to ensure all events have been cleared down * Disable the UART clock to enable the wake-up route through to an interrupt (logic outside UART core) To exit power saving: * Re-enable the UART clock to disable the wake-up route to an interrupt (logic outside UART core) * Perform a read access from the UART to ensure that enough clocks have occurred to update registered versions of the modem status lines. A suitable access with no side-effects would be to read SPR. If modem status is unimportant, the MSR could be read instead * Read the MSR to clear the wake-up signal, subject to no other events occurring. Note: because the event occurred while the clock was turned off, a multiple change (glitch) on any of the modem lines may have triggered the wake-up, but the event may be missed and thus not recorded in the modem status register.
8.7
8.7.1
Modem Interface
Modem Control Register--MCR
MCR[3]: OUT2 logic 0 Force OUT2# output low when loopback mode is disabled. logic 1 Force OUT2# output high. OUT2# is not bonded out in the OXCFU950, but is used internally for loopback testing. MCR[4]: Loopback mode logic 0 Normal operating mode. logic 1 Enable local loop-back mode (diagnostics). In local loop-back mode, the transmitter output (SOUT) and the modem outputs (DTR#, RTS#) are set inactive (high), and the receiver inputs SIN, CTS#, DSR#, DCD#, and RI# are all disabled. Internally the transmitter output is connected to the receiver input and DTR#, RTS#, OUT1# and OUT2# are connected to modem status inputs DSR#, CTS#, RI# and DCD# respectively.
MCR[0]: DTR logic 0 Force DTR# output to inactive (high). logic 1 Force DTR# output to active (low). Note that DTR# can be used for automatic out-of-band flow control when enabled using ACR[4:3] (see section 8.11.3). MCR[1]: RTS logic 0 Force RTS# output to inactive (high). logic 1 Force RTS# output to active (low). Note that RTS# can be used for automatic out-of-band flow control when enabled using EFR[6] (see section 8.9.4). MCR[2]: OUT1 logic 0 Force OUT1# output low when loopback mode is disabled. logic 1 Force OUT1# output high. OUT1# is not bonded out in the OXCFU950, but is used internally for loopback testing.
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In this mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the MCR instead of the four modem status inputs. The interrupts are still controlled by the IER. MCR[5]: Enable XON-Any in enhanced mode or enable out-of-band flow control in non-enhanced mode 650/950 modes (enhanced mode): logic 0 XON-Any is disabled. logic 1 XON-Any is enabled. In enhanced mode (EFR[4]=1), this bit enables the XonAny operation. When Xon-Any is enabled, received data is accepted as a valid Xon (see in-band flow control, section 8.9.3). 750 mode (non-enhanced mode): logic 0 CTS/RTS flow control disabled. logic 1 CTS/RTS flow control enabled. In non-enhanced mode, this bit enables the CTS/RTS outof-band flow control. MCR[6]: IrDA mode logic 0 Standard serial receiver & transmitter data format. logic 1 Data is transmitted & received in IrDA format. This function is only available in enhanced mode. It requires a 16x clock to function correctly. MCR[7]: Baud rate prescaler select logic 0 Normal (divide by 1) baud rate generator prescaler selected. logic 1 Divide-by-M N/8 baud rate generator prescaler selected.
OXCFU950 DATA SHEET
Where M & N are programmed in CPR (ICR offset 0x01). After a hardware reset, CPR defaults to 0x20 (divide-by-4) and MCR[7] is reset to 0. User writes to this flag only take effect in enhanced mode. See section 8.9.1.
8.7.2
Modem Status Register--MSR
MSR[0]: Delta CTS# Indicates that the CTS# input has changed since the last time the MSR was read. MSR[1]: Delta DSR# Indicates that the DSR# input has changed since the last time the MSR was read. MSR[2]: Trailing edge RI# Indicates that the RI# input has changed from low to high since the last time the MSR was read. MSR[3]: Delta DCD# Indicates that the DCD# input has changed since the last time the MSR was read. MSR[4]: CTS This bit is the complement of the CTS# input. It is equivalent to RTS (MCR[1]) during internal loop-back mode. MSR[5]: DSR This bit is the complement of the DSR# input. It is equivalent to DTR (MCR[0]) during internal loop-back mode. MSR[6]: RI This bit is the complement of the RI# input. In internal loopback mode it is equivalent to the internal OUT1. MSR[7]: DCD This bit is the complement of the DCD# input. In internal loop-back mode it is equivalent to the internal OUT2.
8.8
8.8.1
Other Standard Registers
Divisor Latch Registers--DLL & DLM 8.8.2 Scratch Pad Register--SPR
The divisor latch registers are used to program the baud rate divisor. This is a value between 1 and 65535 by which the input clock is divided by in order to generate serial baud rates. After See section 8.10 for full details.
The scratch pad register does not affect operation of the rest of the UART in any way and can be used for temporary data storage. The register may also be used to define an offset value to access the registers in the Indexed Control Register set. For more information on Indexed Control registers see Table 17 and section 8.11.
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OXCFU950 DATA SHEET
8.9
Automatic Flow Control
EFR[3:2]: In-band transmit flow control mode When in-band transmit flow control is enabled, Xon/Xoff characters are inserted into the data stream whenever the RFL passes the upper trigger level and falls below the lower trigger level respectively. For automatic in-band flow control, EFR[4] must be set. The combinations of software transmit flow control can then be selected by programming EFR[3:2] as follows: logic [00] In-band transmit flow control is disabled. logic [01] Single character in-band transmit flow control enabled, using Xon2 as the Xon character and Xoff2 as the Xoff character. logic [10] Single character in-band transmit flow control enabled, using Xon1 as the Xon character and Xoff1 as the Xoff character. Logic[11] The value EFR[3:2] = 11 is reserved for future use and should not be used EFR[4]: Enhanced mode logic 0 Non-enhanced mode. Disables IER[7:4], ISR[5:4], FiCR[5:4], MCR[7:5] and in-band flow control. Whenever this bit is cleared, the setting of other bits of EFR is ignored. logic 1 Enhanced mode. Enables the enhanced mode functions. These functions include enabling IER[7:4], FiCR[5:4], MCR[7:5]. For in-band flow control the software driver must set this bit first. If this bit is set, out-of-band flow control is configured with EFR[7:6], otherwise out-ofband flow control is compatible with 16C750. EFR[5]: Enable special character detection logic 0 Special character detection is disabled. logic 1 While in Enhanced mode (EFR[4]=1), the UART compares the incoming receiver data with the XOFF2 value. Upon a correct match, the received data will be transferred to the RHR and a level 5 interrupt (XOFF or special character) will be asserted if level 5 interrupts are enabled (IER[5] set to 1). EFR[6]: Enable automatic RTS flow control. logic 0 RTS flow control is disabled (default). logic 1 RTS flow control is enabled in enhanced mode (i.e. EFR[4] = 1), where the RTS# pin is forced inactive high if the RFL reaches the upper flow control threshold. This is released when the RFL drops below the lower threshold. The 650 and 950 software drivers should use this bit to enable RTS flow control. The 750 compatible driver uses MCR[5] to enable RTS flow control.
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Automatic in-band flow control, automatic out-of-band flow control and special character detection features can be used in enhanced mode and are software-compatible with the 16C654. Alternatively, 16C750-compatible automatic out-of-band flow control can be enabled in non-enhanced mode. In 950 mode, in-band and out-of-band flow controls are compatible with 16C654, with the addition of fully programmable flow control thresholds.
8.9.1
Enhanced Features Register--EFR
Writing 0xBF to LCR enables access to the EFR and other Enhanced mode registers. This value corresponds to an unused data format. Writing 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. Note: in-band transmit and receive flow control is disabled in 9-bit mode. EFR[1:0]: In-band receive flow control mode When in-band receive flow control is enabled, the UART compares the received data with the programmed Xoff character(s). When this occurs, the UART disables transmission as soon as any current character transmission is complete. The UART then compares the received data with the programmed Xon character(s). When a match occurs, the UART re-enables transmission (see section 8.11.6). For automatic in-band flow control, EFR[4] must be set. The combinations of software receive flow control can be selected by programming EFR[1:0] as follows: logic [00] In-band receive flow control is disabled. logic [01] Single character in-band receive flow control enabled, recognizing Xon2 as the XON character and Xoff2 as the XOFF character. logic [10] Single character in-band receive flow control enabled, recognizing Xon1 as the Xon character and Xoff1 and the Xoff character. logic [11] The behavior of the receive flow control depends on the configuration of EFR[3:2]. Single-character in-band receive flow control is enabled, accepting both Xon1 and Xon2 as valid Xon characters and both Xoff1 and Xoff2 as valid Xoff characters when EFR[3:2] = 01 or 10. EFR[1:0] should not be set to 11 when EFR[3:2] is 00.
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EFR[7]: Enable automatic CTS flow control. logic 0 CTS flow control is disabled (default). logic 1 CTS flow control is enabled in enhanced mode (i.e. EFR[4] = 1), where the data transmission is prevented whenever the CTS# pin is held inactive high. The 650 and 950 software drivers should use this bit to enable CTS flow control. The 750 compatible driver uses MCR[5] to enable CTS flow control.
OXCFU950 DATA SHEET
8.9.2
Special Character Detection
When in-band transmit flow control is enabled, the RFL is sampled whenever the transmitter is idle (briefly, between characters, or when the THR is empty) and an Xon/Xoff character may be inserted into the data stream if needed. Initially, remote transmissions are enabled and hence ASR[1] is clear. If ASR[1] is clear and the RFL has passed the upper trigger level (i.e. is above the trigger level), Xoff is sent and ASR[1] is set. If ASR[1] is set and the RFL falls below the lower trigger level, Xon is sent and ASR[1] is cleared. If transmit flow control is disabled after an Xoff has been sent, an Xon is sent automatically.
In enhanced mode (EFR[4]=1), when special character detection is enabled (EFR[5]=1) and the receiver matches received data with Xoff2, the received special character flag ASR[4] is set and a level 5 interrupt is asserted, if enabled by IER[5]. This flag is cleared following a read of ASR. The received status (i.e. parity and framing) of special characters does not have to be valid for these characters to be accepted as valid matches.
8.9.4
Automatic Out-Of-Band Flow Control
8.9.3
Automatic In-band Flow Control
When in-band receive flow control is enabled, the UART compares the received data with Xoff1 or Xoff2 characters to detect an Xoff condition. When this occurs, the UART disables transmission as soon as any current character transmission is complete. Status bits ISR[4] and ASR[0] are set. A level 5 interrupt occurs, if enabled by IER[5]. The UART then compares all received data with Xon1 or Xon2 characters to detect an Xon condition. When this occurs, the UART re-enables transmission and status bits ISR[4] and ASR[0] are cleared. Any valid Xon/Xoff characters are not written into the RHR, apart from when special character detection is enabled and an Xoff2 character is received that is a valid Xoff. In this instance, the character is written into the RHR. The received status (i.e., parity and framing) of Xon/Xoff characters does not have to be valid for these characters to be accepted as valid matches. When the Xon-Any flag (MCR[5]) is set, any received character is accepted as a valid Xon condition and the transmitter is re-enabled. The received data is transferred to the RHR.
Automatic RTS/CTS flow control is selected by different means, depending on whether the UART is in enhanced or non-enhanced mode. In non-enhanced mode, MCR[5] enables both RTS and CTS flow control. In enhanced mode, EFR[6] enables automatic RTS flow control and EFR[7] enables automatic CTS flow control. This allows software compatibility with both 16C654 and 16C750 drivers. When automatic CTS flow control is enabled and the CTS# input becomes active, the UART disables transmission as soon as any current character transmission is complete. Transmission is resumed whenever the CTS# input becomes inactive. When automatic RTS flow control is enabled, the RTS# pin is forced inactive when the RFL reaches the upper trigger level and returns to active when the RFL falls below the lower trigger level. The automatic RTS# flow control is ANDed with MCR[1] and hence is only operational when MCR[1]=1. This allows the software driver to override the automatic flow control and disable the remote transmitter regardless by setting MCR[1]=0 at any time. Automatic DTR/DSR flow control behaves in the same manner as RTS/CTS flow control but is enabled by ACR[3:2], regardless of whether or not the UART is in enhanced mode.
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OXCFU950 DATA SHEET
8.10 Baud Rate Generation
8.10.1 General Operation
The UART contains a programmable baud rate generator capable of taking the fixed 48-MHz clock input from the OXCFU950 internal PLL and dividing it by any 16-bit divisor number from 1 to 65535 written into the DLM (MSB) and DLL (LSB) registers. In addition, a clock prescaler register is provided which can further divide the clock by values in the range 1.0 to 31.875 in steps of 0.125. A further feature is the Times Clock Register (TCR) which allows the sampling clock to be set to between 4 and 16. These clock options allow for highly-flexible baud rate generation. The actual transmitter and receiver baud rate is calculated as follows:
8.10.2 Clock Prescaler Register--CPR
The CPR register is located at offset 0x01 of the ICR The prescaler divides the system clock by any value in the range of 1 to 31 7/8 in steps of 1/8. The divisor takes the form M + N/8, where M is the 5-bit value defined in CPR[7:3] and N is the 3-bit value defined in CPR[2:0]. The prescaler is by-passed and a prescaler value of 1 is selected by default when MCR[7] = 0. MCR[7] is reset to 0 after a hardware reset but may be overwritten by software. Note: because access to MCR[7] is restricted to enhanced mode only, EFR[4] should first be set and then MCR[7] set or cleared as required. If MCR[7] is set by software, the internal clock prescaler is enabled. Upon a hardware reset, CPR defaults to 0x20 (division-by4). The flexible prescaler allows system designers to generate popular baud rates using clocks that are not integer multiples of the required rate. With the OXCFU950 fixedclock frequency, compatibility with existing 16C550 software drivers may be maintained with a minor software patch to program the on-board prescaler to divide the high frequency clock down to 1.8432 MHz. Table 28 on the following page gives typical TCR, CPR and Divisor values, which can be used to synthesize a range of typical baud rates.
BaudRate =
Where:
InputClock SC * Divisor * prescaler
SC = Sample clock values defined in TCR[3:0] Divisor = (256 x DLM ) + DLL Prescaler = 1 when MCR[7] = 0 else: = M + ( N / 8 ) where: M = CPR[7:3] (Integer part - 1 to 31) N = CPR[2:0] (Fractional part - 0.000 to 0.875 ) See Section 8.10.3 for a discussion of the clock prescaler and times clock register. After a hardware reset, the prescaler is bypassed (set to 1) and TCR is set to 0x00 (i.e. SC = 16). Assuming this default configuration, the following table gives the divisors required to be programmed into the DLL and DLM registers in order to obtain various standard baud rates:
DLM:DLL (Hex) Divisor Word EA 60 6A 88 27 10 13 88 09 C4 04 E2 02 71 01 38 00 9C 00 68 00 4E 00 34 00 1A Baud Rate (bps)) 50 110 300 600 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200
8.10.3 Times Clock Register--TCR
The TCR register is located at offset 0x02 of the ICR The 16C550 and other compatible devices such as 16C654 and 16C750 use a 16 times (16x) over-sampling channel clock. The 16x over-sampling clock means that the channel clock runs at 16 times the selected serial bit rate. It limits the highest baud rate to 1/16 of the system clock when using a divisor latch value of unity. However, the 950 UART is designed to accept other multiplications of the bit rate clock. It can use values from 4x to 16x clock as programmed in the TCR as long as the clock (oscillator) frequency error, stability and jitter are within reasonable parameters. Upon hardware reset the TCR is reset to 0x00 which means that a 16x clock will be used, for compatibility with the 16C550 and compatibles.
Table 26: Standard PC COM Port Baud Rate Divisors
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The OXCFU950 has the facility to operate at baud-rates up to 12 Mbps. This is due to the fixed 48-MHz baud rate and the minimum TCR value of 4. The table below indicates how the value in the register corresponds to the number of clock cycles per bit. TCR[3:0] is used to program the clock. TCR[7:4] are unused and return 0000 if read.
TCR[3:0] 0000 to 0011 0100 to 1111 Clock cycles per bit 16 4-15
OXCFU950 DATA SHEET
The use of TCR does not require the device to be in 650 or 950 mode although only drivers that have been written to take advantage of the 950 mode features are able to access this register. Writing 0x01 to the TCR will not switch the device into 1x isochronous mode--this is explained in the following section. (TCR has no effect in isochronous mode). If 0x01, 0x10 or 0x11 is written to TCR the device operates in 16x mode. Reading TCR always returns the last value that was written to it irrespective of mode of operation. Table 28 shows typical UART baud rates and the register settings which can be used to set them:
Table 27: TCR Sample Clock Configuration
TCR Reg(Bin) 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100
CPR Bits(7:3) 00110 00110 00110 00110 00110 00110 00110 00110 00110 00110 00110 00110 00110 00001 00001 00001 00001 00001
Bits(2:0) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 000 000 000 000
Divisor DLM (Hex) 90 41 18 0C 06 03 01 00 00 00 00 00 00 00 00 00 00 00
DLL(Hex) 3B 8F 09 04 02 01 80 C0 60 40 30 20 10 08 08 04 02 01
Nominal Baud Rate (Bits per sec) 50 110 300 600 1200 2400 4807 9600 19,200 28800 38400 57600 115200 230400 1500000.00 3000000.00 6000000.00 12000000.00
Table 28: Typical Baud Rates and Register Settings to Achieve Them
8.10.4 Alternative Baud Rate Control Registers
Table 18 shows the set of OXCFU950 specific alternative UART baud rate control registers, which can be used instead of the standard versions of these registers. They give the facility to prevent legacy drivers with knowledge of the 950 UART register set from making incorrect assumptions about the OXCFU950 crystal frequency and synthesizing incorrect baud rate values by writing to the standard DLL, DLM, CPR and TCR registers.
Example * Write 0xEB to UART Indirect register 0x30 to enable register access to the alternative register set. * Write new values into A_CPR (0x34) and A_TCR (0x35) UART indirect registers. * Write 0x0C into A_ENABLE (0x31) UART indirect register to enable the alternative CPR and TCR registers. * Write 0x00 to UART Indirect register 0x30 to disable register access to the alternative register set.
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OXCFU950 DATA SHEET
8.11 Additional Features
8.11.1 Additional Status Register--ASR
ASR[0]: Transmitter disabled logic 0 The transmitter is not disabled by in-band flow control. logic 1 The receiver has detected an Xoff, and has disabled the transmitter. This bit is cleared after a hardware reset or channel software reset. The software driver may write 0 to this bit to re-enable the transmitter if it was disabled by in-band flow control. Writing 1 to this bit has no effect. ASR[1]: Remote transmitter disabled logic 0 The remote transmitter is not disabled by inband flow control. logic 1 The transmitter has sent an Xoff character, to disable the remote transmitter. (Cleared when a subsequent Xon is sent). This bit is cleared after a hardware reset or channel software reset. The software driver may write 0 to this bit to re-enable the remote transmitter (an XON is transmitted). Writing 1 to this bit has no effect.
Note: The remaining bits (ASR[7:2]) of this register are read only
ASR[5]: RESERVED This bit is unused in the OXCFU950 and reads 0. ASR[6]: FIFO size logic 0 FIFOs are 16 deep if FiCR[0] = 1. logic 1 FIFOs are 128 deep if FiCR[0] = 1. Note: If FiCR[0] = 0, the FIFOs are 1 deep. ASR[7]: Transmitter Idle logic 0 Transmitter is transmitting. logic 1 Transmitter is idle. This bit reflects the state of the internal transmitter. It is set when both the transmitter FIFO and shift register are empty.
8.11.2 FIFO Fill levels--TFL & RFL
The TFL and RFL registers can be accessed in both the 950-specific registers and the OXCFU950-specific registers; the latter is the most direct means of access. The number of characters stored in the THR and RHR can be determined by reading the TFL and RFL registers respectively. As the UART clock is asynchronous with respect to the processor, it is possible for the levels to change during a read of these FIFO levels. It is therefore recommended that the levels are read twice and compared to check that the values obtained are valid. The values should be interpreted as follows: 1. 2. The number of characters in the THR is no greater than the value read back from TFL. The number of characters in the RHR is no less than the value read back from RFL.
ASR[2]: RTS This is the complement of the actual state of the RTS# pin when the device is not in loopback mode. The driver software can determine whether the remote transmitter is disabled by RTS# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin's actual state. ASR[3]: DTR This is the complement of the actual state of the DTR# pin when the device is not in loopback mode. The driver software can determine whether the remote transmitter is disabled by DTR# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin's actual state.
8.11.3 Additional Control Register--ACR
The ACR register is located at offset 0x00 of the ICR ACR[0]: Receiver disable logic 0 The receiver is enabled, receiving data and storing it in the RHR. logic 1 The receiver is disabled. The receiver continues to operate as normal to maintain the framing synchronization with the receive data stream, but received data is not stored into the RHR. In-band flow control characters continue to be detected and acted upon. Special characters are not detected. Changes to this bit are only recognized following the completion of any data reception pending.
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ASR[4]: Special character detected
logic 0 No special character has been detected. logic 1 A special character has been received and is stored in the RHR. This can be used to determine whether a level 5 interrupt was caused by receiving a special character rather than an Xoff. The flag is cleared following the read of the ASR.
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ACR[1]: Transmitter disable logic 0 The transmitter is enabled, transmitting any data in the THR. logic 1 The transmitter is disabled. Any data in the THR is not transmitted but is held. However, in-band flow control characters may still be transmitted. Changes to this bit are only recognized following the completion of any data transmission pending. ACR[2]: Enable automatic DSR flow control logic 0 Normal. The state of the DSR# line does not affect the flow control. logic 1 Data transmission is prevented whenever the DSR# pin is held inactive high. This bit provides another automatic out-of-band flow control facility using the DSR# line. ACR[4:3]: DTR# line configuration The DTR# pin is defined as follows: logic [00] DTR# is compatible with 16C450, 16C550, 16C654 and 16C750 (i.e. normal). logic [01] DTR# pin is used for out-of-band flow control. It is forced inactive high if the RFL reaches the upper flow control threshold. DTR# line is re-activated when the RFL drops below the lower threshold (see FCL & FCH). logic [10] DTR# pin is configured to drive the active low enable pin of an external RS485 buffer. In this configuration the DTR# pin will be forced low whenever the transmitter is not empty (LSR[6]=0), otherwise DTR# pin is high. logic [11] DTR# pin is configured to drive the activehigh enable pin of an external RS485 buffer. In this configuration, the DTR# pin will be forced high whenever the transmitter is not empty (LSR[6]=0), otherwise DTR# pin is low. If the user sets ACR[4], the DTR# line is controlled by the status of the transmitter empty bit of LCR. When ACR[4] is set, ACR[3] is used to select active-high or active-low enable signals. In half-duplex systems using RS485 protocol, this facility enables the DTR# line to directly control the enable signal of external 3-state line driver buffers. When the transmitter is empty the DTR# would go inactive once the SOUT line returns to its idle marking state.
OXCFU950 DATA SHEET
ACR[5]: 950 mode trigger levels enable logic 0 Interrupts and flow control trigger levels are as described in FiCR register and are compatible with 16C654/16C750 modes. logic 1 950 specific enhanced interrupt and flow control trigger levels defined by RTL, TTL, FCL and FCH are enabled. ACR[6]: ICR read enable logic 0 The LSR is readable. logic 1 The ICRs are readable. Setting this bit maps the ICR set to the LSR location for reads. During normal operation this bit should be cleared. ACR[7]: Additional status enable logic 0 Access to the ASR, TFL and RFL registers is disabled. logic 1 Access to the ASR, TFL and RFL registers is enabled. When ACR[7] is set, the MCR and LCR registers are no longer readable but remain writable, and the TFL and RFL registers replace them in the memory map for read operations. The IER register is replaced by the ASR register for all operations. The software driver may leave this bit set during normal operation, since MCR, LCR and IER do not generally need to be read.
8.11.4 Transmitter Trigger Level--TTL
The TTL register is located at offset 0x04 of the ICR Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4 and 5 of FiCR are ignored and an alternative arbitrary transmitter interrupt trigger level can be defined in the TTL register. This 7-bit value provides a fully programmable transmitter interrupt trigger facility. In 950 mode, a priority level 3 interrupt occurs indicating that the transmitter buffer requires more characters when the interrupt is not masked (IER[1]=1) and the transmitter FIFO level falls below the value stored in the TTL register. The value 0 (0x00) has a special meaning. In 950 mode when the user writes 0x00 to the TTL register, a level 3 interrupt only occurs when the FIFO and the transmitter shift register are both empty and the SOUT line is in the idle marking state. This feature is particularly useful to report back the empty state of the transmitter after its FIFO has been flushed away.
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OXCFU950 DATA SHEET
8.11.5 Receiver Interrupt. Trigger Level--RTL
The RTL register is located at offset 0x05 of the ICR Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6 and 7 of FiCR are ignored and an alternative arbitrary receiver interrupt trigger level can be defined in the RTL register. This 7-bit value provides a fully programmable receiver interrupt trigger facility as opposed to the limited trigger levels available in 16C654 and 16C750 devices. It enables the system designer to optimize the interrupt performance hence minimizing the interrupt overhead. In 950 mode, a priority level 2 interrupt occurs indicating that the receiver data is available when the interrupt is not masked (IER[0]=1) and the receiver FIFO level reaches the value stored in this register.
CTS/RTS and DSR/DTR out-of-band flow control use the same trigger levels as in-band flow control. When out-ofband flow control is enabled, RTS# (or DTR#) line is deasserted when the receiver FIFO level reaches the upper limit defined in the FCH and is re-asserted when the receiver FIFO is drained below the lower limit defined in FCL. When 950 trigger levels are enabled (ACR[5]=1), the CTS# flow control functions as in 650 mode and is configured by EFR[7]. However, when EFR[6] is set, RTS# is automatically de-asserted when RFL reaches FCH and re-asserted when RFL drops below FCL. DSR# flow control is configured with ACR[2]. DTR# flow control is configured with ACR[4:3].
8.11.7 Device Identification Registers
The identification registers is located at offsets 0x08 to 0x0B of the ICR The 950 offers four bytes of device identification. The device identification registers may be read using offset values 0x08 to 0x0B of the Indexed Control Register. Registers ID1, ID2 and ID3 identify the device as an OX16C950 type and return 0x16, 0xC9 and 0x50 respectively. The REV register resides at offset 0x0B of ICR and identifies the revision of CFU950 UART core. This register returns 0x11 for the OXCFU950.
8.11.6 Flow Control Levels--FCL & FCH
The FCL and FCH registers are located at offsets 0x06 and 0x07 of the ICR respectively Enhanced software flow control using Xon/Xoff and hardware flow control using RTS#/CTS# and DTR#/DSR# are available when 950 mode trigger levels are enabled (ACR[5]=1). Improved flow control threshold levels are offered using Flow Control Lower trigger level (FCL) and Flow Control Higher trigger level (FCH) registers to provide a greater degree of flexibility when optimizing the flow control performance. Generally, these facilities are only available in enhanced mode. In 650 mode, in-band flow control is enabled using the EFR register. An Xoff character is transmitted when the receiver FIFO exceeds the upper trigger level defined by FiCR[7:6] as described in section 8.4.2. An Xon is then sent when the FIFO is read down to the lower fill level. The flow control is enabled and the appropriate mode selected using EFR[3:0]. In 950 mode, the flow control thresholds defined by FiCR[7:6] are ignored. In this mode threshold levels are programmed using FCL and FCH. When in-band flow control is enabled (defined by EFR[3:0]) and the RFL) reaches the value programmed in the FCH register, an Xoff is transmitted to stop the flow of serial data. The flow is resumed when the receiver FIFO fill level falls to below the value programmed in the FCL register, at which point an Xon character is sent. The FCL value of 0x00 is illegal. For example if FCL and FCH contain 64 and 100 respectively, Xoff is transmitted when the receiver FIFO contains 100 characters, and Xon is transmitted when sufficient characters are read from the receiver FIFO such that 63 characters remain.
8.11.8 Nine-bit Mode Register--NMR
The NMR register is located at offset 0x0D of the ICR The 950 offers 9-bit data framing for industrial multi-drop applications. 9-bit mode is enabled by setting bit 0 of the nine-bit mode register (NMR). In 9-bit mode the data length setting in LCR[1:0] is ignored. Furthermore as parity is permanently disabled, the setting of LCR[5:3] is also ignored. The receiver stores the 9th bit of the received data in LSR[2] (where parity error is stored in normal mode). Note that the 950 provides a 128-deep FIFO for LSR[3:1]. The transmitter FIFO is 9-bit wide and 128 deep. The user should write the 9th (MSB) data bit in SPR[0] first and then write the other 8 bits to THR. As parity mode is disabled, LSR[7] is set whenever there is an overrun, framing error or received break condition. It is unaffected by the contents of LSR[2] (Now the received 9th data bit). In 9-bit mode, in-band flow control is disabled regardless of the setting of EFR[3:0] and the Xon1/Xon2/Xoff1 and Xoff2 registers are used for special character detection.
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Interrupts in 9-Bit Mode:
While IER[2] is set, on receiving a character with status error, a level 1 interrupt is asserted when the character and the associated status are transferred to the FIFO. The 950 can assert an optional interrupt if a received character has its 9th bit set. As multi-drop systems often use the 9th bit as an address bit, the receiver is able to generate an interrupt upon receiving an address character. This feature is enabled by setting NMR[2]. This results in a level 1 interrupt being asserted when the address character is transferred to the receiver FIFO. In this case, as long as there are no errors pending, i.e. LSR[1], LSR[3], and LSR[4] are clear, 0 can be read back from LSR[7] and LSR[1], thus differentiating between an address interrupt and receiver error or overrun interrupt in 9-bit mode. Note: if an overrun or error interrupt actually occurs, an address character may also reside in the FIFO. In this case, the software driver should examine the contents of the receiver FIFO as well as process the error. The above facility produces an interrupt for recognizing any address characters. Alternatively, users can configure the OXCFU950 UART to match the receiver data stream with up to four programmable 9-bit characters and assert a level 5 interrupt after detecting a match. The interrupt occurs when the character is transferred to the FIFO (See below). NMR[0]: 9-bit mode enable logic 0 9-bit mode is disabled. logic 1 9-bit mode is enabled. NMR[1]: Enable interrupt when 9th bit is set logic 0 Receiver interrupt for detection of an address character (i.e. 9th bit set) is disabled. logic 1 Receiver interrupt for detection of an address character (i.e. 9th bit set) is enabled and a level 1 interrupt is asserted.
NMR[7:6]: Reserved Bits 6 and 7 of NMR are always cleared and reserved for future use.
8.11.9 Modem Disable Mask--MDM
The MDM register is located at offset 0x0E of the ICR This register is cleared after a hardware reset to maintain compatibility with 16C550. It allows the user to mask interrupts and control UART power saving operation due to individual modem lines or the serial input line. Note: UART power saving is controlled from outside the UART. See 8.6.4. MDM[0]: Disable delta CTS logic 0 Delta CTS is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Delta CTS can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta CTS is disabled. It can not generate an interrupt or wake up the UART. MDM[1]: Disable delta DSR logic 0 Delta DSR is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Delta DSR can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta DSR is disabled. In can not generate an interrupt or wake up the UART. MDM[2]: Disable Trailing edge RI logic 0 Trailing-edge RI is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Trailing-edge RI can wake up the UART when it is asleep under auto-sleep operation. logic 1 Trailing-edge RI is disabled. In can not generate an interrupt or wake up the UART. MDM[3]: Disable delta DCD logic 0 Delta DCD is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Delta DCD can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta DCD is disabled. In can not generate an interrupt or wake up the UART. MDM[4]: Disable wake-up sensitivity logic 0 Enables wake-ups based on the sensitivity settings of MDM[3:0] logic 1 Disables all wake-ups. MDM[7:3]: Reserved These bits must be set to 0000
Special Character Detection
While the UART is in both 9-bit mode and enhanced mode, setting IER[5] enables detection of up to four address characters. The least significant eight bits of these four programmable characters are stored in special characters 1 to 4 (Xon1, Xon2, Xoff1 and Xoff2 in 650 mode) registers and the 9th bit of these characters are programmed in NMR[5] to NMR[2] respectively. NMR[2]: NMR[3]: NMR[4]: NMR[5]: Bit 9 of Special Character 1 Bit 9 of Special Character 2 Bit 9 of Special Character 3 Bit 9 of Special Character 4
8.11.10 Readable FiCR--RFC
The RFC register is located at offset 0x0F of the ICR This read-only register returns the current state of the FiCR register (Note: FiCR is write-only). This register is included for diagnostic purposes.
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8.11.11 Good-data status register--GDS
The GDS register is available directly in OXCFU950 specific register space at 0x0F. It is also accessible at offset 0x10 of the ICR. Good data status is set when the following conditions are true: * ISR reads level0 (no interrupt), level2 or 2a (receiver data) or level3 (THR empty) interrupt. * LSR[7] is clear i.e. no parity error, framing error or break in the FIFO. * LSR[1] is clear i.e. no overrun error has occurred. GDS[0]: Good Data Status GDS[7:1]: Reserved
8.11.14 Alternative UART Baud Rate Control Registers: A_LATCH, A_ENABLE, A_DLL, A_DLM, A_CPR, A_TCR
Table 18 shows the set of OXCFU950-specific alternative UART baud rate control registers, which can be used instead of the standard versions of these registers. This facility prevents legacy drivers with knowledge of the 950 UART register set from making incorrect assumptions about the OXCFU950 crystal frequency and synthesize incorrect baud rate values by writing to the standard DLL, DLM, CPR and TCR registers. See 8.10.4 for further details.
8.11.15 Alternative 32-Bit FIFO Access Enable:
DBURST
8.11.12 DMA Status Register--DMS
The DMS register is located at offset 0x11 of the ICR. This register is unused in the OXCFU950 except for test purposes.
Table 18 shows the DBURST, the Alternative 32-bit FIFO Access Registers Enable. The 32-bit FIFO Access registers can be accessed at 0x00 through 0x03, when DBURST is set to 0x01. This is for systems where the UART must be mapped to an8-byte address space. See 8.4.1 for further details.
8.11.13 Port Index Register--PIX
The PIX register is located at offset 0x12 of the ICR. This read-only register gives the UART index. For a single channel device such as the OXCFU950 this reads 0.
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9
MULTI PURPOSE I/O (MIO) AND USB POWER MANAGEMENT MODULE
The OXCFU950 supports four multi-purpose I/Os (MIOs) for general applications which are fully configurable/controllable by software. Such applications may be used to control external devices via a serial interface, or act as a status monitor of external circuits, for example. The MIO pins can be configured as inputs or outputs, and can cause a general purpose interrupt to be generated (individually generated for each MIO pin). In addition, in input mode, the active state can be set to logic '1' or logic '0' for additional flexibility. Refer to the Multi-purpose I/O Configuration description (offset 0x11) and MIO interrupt Enable Register description (offset 0x13) for a description of the MIO pins configuration. See section 6.5 for further details. In addition to the normal MIO operation, MIO[3:2] can be configured to be used as power management pins, with the use of an external circuit, to provide USB bus power generation (VBUS) and over-current detection as described in the USB Specification. Refer to Soft USB Reset and Clock Enable Register (offset 0x17) in section 6.5 for further details.
10 INTERNAL EEPROM SPECIFICATION
The OXCFU950 can be configured using its on-board EEPROM. If the EEPROM does not contain a valid image, the device remains in its default configuration after reset. Although this may be adequate for some purposes, normal functional operation requires at least a partial image in the EEPROM. The EEPROM also allows accesses to the integrated UART and USB host controller, which can be useful for default setups. The OXCFU950 device includes 512 bytes of internal EEPROM. This allows the device to be configured in the following ways: 1) The CIS can be modified to allow customers to differentiate their products. 2) The registers in I/O space can be written to allow the UART function to be setup in a specific way after a power on, hard or soft reset. 3) The registers in I/O space can be written to allow the USB function to be setup in a specific way after a power on, hard or soft reset. A zone type system is used to tell the device which areas of the device are being programmed. If only one area is being programmed by the EEPROM, the programming time is reduced by only enabling that particular zone to be downloaded (encoded in header in EEPROM). The EEPROM download occurs at three possible times during the PC Card operation: * Following a power-up of card (after insertion of the card into a socket) * Following a hard reset, from the RESET pin on the PC Card / CF interface. * After a soft reset (either USB or UART) a partial reset of the card should take place as follows: o Following a soft reset (via the UART COR soft reset bit) the UART FCR is reset, as is the UART. The UART register access zone should then be executed, if present. o Following a soft reset of the UART (via the LCR) the UART is reset, and the UART register access zone should then be executed, if present. The UART FCR is not reset. o Following a soft reset (via the USB COR soft reset bit) the USB FCR is reset, as is the USB host controller. The USB register access zone should then be executed, if present. o Following a soft reset of the USB (via the LCR) the USB host controller is reset, and the USB register access zone should then be executed, if present. The USB FCR is not reset. When one of these conditions occurs, the EEPROM controller detects whether a valid image is present on the EEPROM. If no valid image is present, the download is not performed and the default values (for attribute tuple data, etc) are selected.
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During the download period the READY# line is kept high to hold off the host from interrogating the card. This is required because if normal interrogation was permitted during an EEPROM download, incorrect data may be read by the host causing error in configuration or even a graceful rejection of the card by the host. The EEPROM can be programmed from the CF/PC Card Interface. When the EEPROM has been programmed, a PCMCIA reset or function reset must be performed to load in the new values and configure the CF950 to the required state. If an invalid CIS is downloaded to the OXCFU950, the host may gracefully reject the card. This means that the card is no longer accessible via the host, and the EEPROM can not be reprogrammed. However, by using the CIS_MODE pin to select the default CIS, it is possible enumerate the card, and the EEPROM can be reprogrammed. To allow an EEPROM download to take place the CIS_MODE pin must be held HIGH. To stop the EEPROM download taking place the CIS_MODE pin will be held LOW. The zones included for the EEPROM download are described below. First of all a header 16 value is read in. If it is a valid value then the EEPROM controller detects from this byte which zones are included in the download. It then reads in each zone of data and passes it to the relevant area in the OXCFU950 (i.e. CIS memory, function or local registers). When all the zones have been loaded into the relevant area, the download is complete.
10.1 Zone 0 : Zone Header
The zone header is the first value to be read and is at address 0 in the EEPROM. It has the following format:
Bits 15:4 2 1 0 Description These bits should return 0xF87 to identify a valid program. 1--Zone 1 (CIS Configuration) data exists 0--Zone 1 does not exist 1--Zone 2 (USB Function Access) data exists 0--Zone 2 does not exist 1--Zone 3 (UART Function Access) data exists 0--Zone 3 does not exist
Table 26. Zone 0 format The programming data for each zone follows the preceding zone if it exists. For example, a header value of 0xF877 indicates that all zones exist and they follow one another, while 0xF876 indicates that only zone 1 and zone 2 exist.
10.2 Zone 1 : CIS Configuration Zone
This zone allows the user to provide custom tuple information for the card information structure, overriding the default hardcoded tuple values found in the device. Downloading into this zone programs the internal RAM with the user's tuple data and automatically sets the source of the CIS to be this RAM. Tuple data bytes are read until the specified number of type data-bytes have been collected in which case the EEPROM moves over to the next zone if it exists, or the EEPROM download terminates if no other zones are present. The zone contains data to be downloaded into the attribute memory (RAM address 0 to 255, attribute memory addresses 0 to 510, even locations only). The first WORD in this zone describes how many bytes of data are present to be downloaded. The next words contain the tuple data for the attribute memory.
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Byte Number 1st WORD 2nd WORD 3rd WORD (N + 1) th WORD 15 "00000000" Attribute Mem.Tuple Byte 1 Attribute Mem.Tuple Byte 3 Attribute Mem.Tuple Byte N-1 8
OXCFU950 DATA SHEET
Description 7 0 Number of tuple bytes in Attribute Memory (M) Note : Must be a value of multiple of 2 Attribute Mem.Tuple Byte 0 Attribute Mem.Tuple Byte 2 Attribute Mem.Tuple Byte N-2
Table 27. Zone 1 Format The EEPROM controller outputs a flag to signify whether a new CIS has been downloaded from the EEPROM. This allows the memory controller to select between the default CIS or the new CIS from the EEPROM.
10.3 Zone 2 : USB Function Access zone.
This zone of the EEPROM contains information required to do any vendor-specific setup of the chip for USB operation. 8-bit values can be written to any valid location in I/O space. Therefore this zone can set up the UART, USB and LCR if required. This zone is executed if present on a hard reset, or a USB soft reset (via LCR or FCR). Care should be taken that the contents of zone 2 and zone 3 are compatible, and do not conflict with each other.
Bits 15 14:8 7:0 Description 0--no more configuration WORDs to follow in zone 2. Move to next available zone or end EEPROM program if no more zones are enabled in the header. 1--another configuration WORD follows for the local configuration registers I/O space address. 8-bit value of the register to be programmed
Table 28. Zone 2 Format
10.4 Zone 3 : UART Function Access
This zone of the EEPROM contains information required for any vendor-specific setup of the chip for UART operation. 8-bit values can be written to any valid location in I/O space. Therefore this zone can set up the UART, USB and LCR if required. This zone is executed if present on a hard reset, or a UART soft reset (via LCR or FCR). Care should be taken that the contents of zone 2 and zone 3 are compatible, and do not conflict with each other.
Bits 15 14:8 7:0 Description 0--no more configuration WORDs to follow in Zone 2. Move to next available zone or end EEPROM program if no more zones are enabled in the header. 1--another configuration WORD follows for the local configuration registers I/O space address. 8-bit value of the register to be programmed
Table 29. Zone 3 Format
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11 INTRODUCTION TO THE OXCFU950 SOFTWARE DRIVERS
This section gives a brief overview of the organization and usage of software drivers for the OXCFU950 operating in the Microsoft Windows XPTM environment. The following figure illustrates the driver stack that is created in Windows XP for the OXCFU950 drivers. Once the device is inserted, the PCMCIA bus driver (pcmcia.sys) drives Multi-Function driver (mf.sys), and it loads both the UART(oxser.sys) and USB (oxcfu950.sys) driver.
Application/ Device Driver
4
USB client driver
3
USB driver oxcfu950.sys
UART Serial Bus Driver oxser.sys
2
Multifunction bus driver mf.sys
Key Oxford Semiconductor Driver System Supplied Driver
1
PCMCIA bus driver pcmcia.sys
Figure 1.1 OXCFU950 Driver Stack on Windows XP Starting from the bottom of the figure, the following describes each driver in the stack: 1. At the bottom of the driver stack tree is the PCMCIA driver pcmcia.sys which is a built-in driver of Windows XP. The PCMCIA driver, pcmcia.sys detects the OXCFU950 device when the card is inserted, and reports the device details described in attribute memory in the OXCFU950. Because the OXCFU950 complies with the PC Card multifunction standard, the Multi-Function driver, mf.sys is automatically loaded after PCMCIA 16-bit PC Card or CompactFlash/ CF+card is inserted. 2. The Multi-Function driver, mf.sys allows both functions to communicate with the hardware independently and defines a range of I/O resources that are exclusive to each function. Once the mf.sys is loaded by pcmcia.sys, mf.sys enumerates the functions such as Device 0 (which is the UART Port), and the Device1(which is the USB Controller) and thereby causes the Plug and Play (PnP) Manager to load individual function drivers. mf.sys is installed by the system supplied inf file, mf.inf. The Multi-function driver, mf.sys enables the individual device drivers to access individual hardware resources without any interaction with each other. The OXCFU950 is driven by two individual drivers, The UART port is driven by the oxser.sys and the USB port is driven by the oxcfu950.sys. The UART driver oxser.sys has an interface compatible with built-in Microsoft COM port driver, serial.sys, and the USB driver oxcfu950.sys has an interface compatible with built-in Microsoft USB driver, usbhub.sys. The drivers at level 4 in the diagram can access the supplied Oxford Semiconductor driver using the same I/O request codes that are used for the built in Microsoft equivalents.
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oxser.sys should be installed by OXSER.INF, and oxcfu950.sys should be installed by OXCFU950.INF. These INF files are provided in OXCFU950 driver package. 4. Each particular USB device is supported by a USB client driver. USB client device drivers for devices are layered directly above the oxcfu950.sys.
12 OPERATING CONDITIONS
Symbol VDD VIN IOUT TSTG Parameter DC supply voltage DC input voltage DC output current Storage temperature Table 29: Absolute Maximum Ratings Symbol VDD TO Parameter DC supply voltage Operating Temperature range Min 2.85 -40 Max 3.6 85 Units V C Min. -0.3 -0.3 -55 Max. 3.8 VDD + 0.3 +/- 10 125 Units V V mA C
Table 30: Recommended Operating Conditions
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13 DC ELECTRICAL CHARACTERISTICS
13.1 2.85 V to 3.6 V Operation
OXCFU950 IO Operation at 3.3 V, 2.5 V & 1.8 V 3.3 Volts Parameter Conditions Min 3.3V I/Os 2.85 Low Level Input Voltage -0.3 High Level Input Voltage Low Level Output Voltage High Level Output Voltage Operating supply current in normal mode Operating supply current in sleep mode 2.5 Volts Parameter 2.5V I/Os Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage 1.8 Volts Parameter 1.8V I/Os Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage 2.0 IOL = 2 mA IOH= 2 mA VDD3.3 - 0.4 13.0 4.0 UART & MIO Pin Groups Only Conditions Min 2.25 -0.25 1.7 IOL = 1 mA IOH= 1 mA VDD2.5 - 0.30 UART & MIO Pin Groups Only Conditions Min 1.65 -0.18 0.65 * VDD1.8 IOL = 0.35 mA IOH= 0.35 mA VDD1.8 - 0.20
Symbol VDD3.3 VIL VIH VOL VOH
Max 3.60 +0.8 VDD3.3 + 0.3
Note 1
Unit V V V V V mA mA
0.4
ICC ICC
Symbol VDD2.5 VIL VIH VOL VOH Symbol VDD1.8 VIL VIH VOL VOH
Max 2.75 +0.7 VDD2.5 + 0.25
Note 1
Unit V V V V V Unit V V V V V
0.30
Max 1.95 0.35 * VDD1.8 VDD1.8 + 0.18 #1 0.20
Table 31: DC Electrical Characteristics
Note 1: These I/Os are 5V-tolerant
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14 TIMING WAVEFORMS / AC CHARACTERISTICS
14.1 Memory Access
tsu(A) A[3:0], REG# tsu(CE) ta(OE) tdis(OE) VALID DATA th(CE) th(A)
CE1#
OE#
D[7:0]
WE#, IORD#, IOWR#, RESET# = 1
Figure 3: Attribute/Common Memory Read Timing
tsu(A) A[3:0], REG# tsu(CE)
th(A)
th(CE)
CE1#
OE#
WE# th(D) D[7:0] (Din) tdis(OE) D[7:0] (Dout)
IORD#, IOWR#, RESET# = 1
Figure 4: Attribute/Common Memory write timing
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Symbol tsu(A) tsu(CE) ta(OE) tdis(OE) th(D) th(A) th(CE) Read Access Min (ns) TBD TBD TBD TBD TBD TBD
OXCFU950 DATA SHEET
Max (ns) TBD TBD TBD TBD TBD TBD
Write Access Min (ns) TBD TBD TBD TBD TBD TBD
Max (ns) TBD TBD TBD TBD TBD TBD
Table 32: Memory Access Timing Specification
14.2 I/O Access
tsu A (IORD) A[3:0] REG# tsu REG (IORD) tsu CE (IORD) td(IORD) th(IORD) VALID DATA
CE1#
IORD#
D[7:0]
OE#, WE#, IOWR#, RESET# = 1
Figure 5: I/O read timing
tsu A (IOWR) A[3:0] tsu REG (IOWR) tsu CE (IOWR)
REG#
CE1#
IOWR#
th(IOWR)
D[7:0] tsu(IOWR) OE#, WE#, IORD#, RESET# = 1
Figure 6: I/O write timing
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Symbol tsu A (IORD) tsu REG (IORD) tsu CE (IORD) td(IORD) th(IORD) tsu A (IOWR) tsu REG (IOWR) tsu CE (IOWR) tsu(IOWR) th(IOWR)
Read Access Min (ns) TBD TBD TBD TBD
Max (ns)
Write Access Min (ns)
Max (ns)
TBD TBD TBD TBD TBD TBD Table 33: I/O Access Timing Specification
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15 PACKAGE INFORMATION
ccc A D aaa C A bbb C B A A2 A3 A1 0.10
A
E
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
B
C
SEATING PLANE
TOP VIEW
SIDE VIEW
D2 0.55
R
Pin 1 ID 0.20 R 0.45 0.55 b 0.10 M C A B e L
L
BOTTOM VIEW
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15.1 Package Dimensions
Millimeter Nom A --A1 --A2 0.65 A3 0.20 REF. b 0.23 0.25 D 9.00 bsc D2 6.95 7.10 E 9.00 bsc E2 6.95 7.10 L 0.35 0.40 e 0.50 bsc R 0.125 --Tolerances of Form and Position aaa 0.10 bbb 0.10 ccc 0.05 Symbol Min -------
Max 0.90 0.05 0.70 0.28 7.25 7.25 0.45 ---
Min ------0.009 0.274 0.274 0.014 0.005
Inch Nom ----0.026 0.008 REF. 0.010 0.354 bsc 0.280 0.354 bsc 0.280 0.016 0.020 bsc --0.004 0.004 0.002
Max 0.035 0.001 0.028 0.011 0.285 0.285 0.018 ---
16 ORDERING INFORMATION
OXCFU950-QFAG
Green (RoHS-compliant) Revision Package Type-QF
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NOTES
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CONTACT DETAILS
Oxford Semiconductor 1900 McCarthy Boulevard, Suite 210 Milpitas, CA 95035 USA
Sales e-mail: Web site:
sales@oxsemi.com http://www.oxsemi.com
DISCLAIMER
Oxford Semiconductor, Inc. believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. No responsibility is assumed by Oxford Semiconductor, Inc. for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of Oxford Semiconductor, Inc. Oxford Semiconductor terms and conditions of sale apply at all times.
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